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SiP, PVS tech enabled for TSMC InFO packaging

Posted: 28 Sep 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design Systems? Allegro? SiP? PVS? InFO?

Cadence Design Systems, Inc. has revealed that its Allegro System-in-Package (SiP) and Physical Verification System (PVS) implementation technologies have been enabled for TSMC's Integrated Fan-Out (InFO) packaging technology. The Allegro SiP design tools and PVS allow TSMC customers to slash the InFO design and verification cycle by offering an integrated solution that automates the design-rule checking (DRC) flow, stated the company.

TSMC's InFO advanced wafer-level packaging technology claims to offer cost-effective system scaling to boost system bandwidth, while reducing power consumption and device form factors. Compared to other methodologies, InFO is intended for mobile and Internet of Things (IoT) applications.

In collaborating with TSMC for this enablement, Cadence developed novel IC packaging technology in Allegro SiP Layout to address InFO-specific design requirements, and provided features that allow designers to meet and verify the design rules, layout structures and metal density requirements of an InFO design. Cadence tailored the mask-generation technology to accurately represent the InFO design structures in GDSII, allowing designers to verify the accuracy of the mask prior to submission to TSMC for fabrication.





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