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Protocol exerciser/analyser aimed at PCIe 4.0 design

Posted: 02 Oct 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Teledyne LeCroy? protocol exerciser? analyser? PCIe 4.0?

Teledyne LeCroy has introduced its PCI Express (PCIe) protocol exerciser/analyser for testing PCI Express 4.0 designs and products. According to the company, the Summit Z416 exerciser/analyser targets the needs of PCI Express developers by offering high performance 16GT/s traffic generation on devices with link widths up to 16 lanes.

In addition to traffic generation, protocol analysis featuring Teledyne LeCroy's industry-standard CATC Trace and other traffic displays and data reports are available. The Summit Z416 supports exerciser functions that can be used for traffic generation and device/host emulation, as well as providing the industry a platform for development of standardized compliance test suites. Additionally, the Summit Z416 support error injection functions to enable developers to test error recovery routines important to reliable interoperability of PCIe 4.0 products.

Protocol analysers and exercisers are key tools to help driver and firmware developers understand serial data communication between their devices and systems. The Summit Z416 features a unified single application that incorporates traffic generation and protocol analysis. A protocol exerciser is an important part of protocol development and specification corner case testing. It provides realistic traffic to devices under test and can also emulate complex host- or device-side traffic while the protocol analyser acquires, records, decodes, analyses and displays complex high-speed PCI Express I/O streams. Users will have access to analysis and reporting capabilities that are highly utilised in the PCIe industry. When analysers and exercisers are used together developers can create powerful script level traffic and monitor the results of all tests.

The Summit Z416 will allow developers to work on bringing up LTSSM and dynamic equalisation structures during the early power-on phase of development. Features addressing this include providing bus traffic to emulate the beginning Polling and Detect states, through the equalisation phases to the final link up at the L0 state and maintaining the L0 state between the host and device. Automatic skip generation is provided and received packets will be ACKed. The exerciser will support lane reversal and control polarity and scrambling. An important feature to note is that traffic emulation supports not only dynamic equalisation but also Skip EQ training in order to handle full autonomous speed switch between all combinations of speeds. The exerciser also has the capability to perform error injection on either a packet or per lane basis.

Along with the Summit Z416 Teledyne LeCroy is also releasing a Gen4 test platform that is a two CEM-socket backplane capable of supporting 16GT/s bus transactions for testing CEM form factor devices with the Gen4 test platform. Two test fixtures are being made available to help with testing PCIe 4.0 devices: a PCI Express Verification Load Board (VLB) for testing PCI Express platforms, and the PCI Express Validation Base Board (VBB) for testing PCI Express Add-in Cards. Each of these test tools will aid developers in electrical test, functional verification, interoperability and performance testing for PCIe 4.0 products.

All Teledyne LeCroy protocol analysis and test products feature a hierarchical display, real-time statistics, protocol traffic summaries, detailed error reports, powerful scripting, and the ability to create user-defined test reports, which allow developers to troubleshoot intricate problems and finish their projects on time, stated the company. Users of Teledyne LeCroy systems appreciate the rich library of decodes and analysis capabilities that are available on all of Teledyne LeCroy's PCIe test tools.

The Summit Z416 PCIe 4.0 protocol exerciser/analyser is available to order.





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