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Laying down the scaling path for monolithic 3D

Posted: 14 Oct 2015 ?? ?Print Version ?Bookmark and Share

Keywords:monolithic 3D? ELTRAN? Qualcomm? IBM? Leti?

The 2015 IEEE S3S Monolithic 3D: Game-Changing 2.0 has underscored the idea that using a novel technique, a substrate could be prepared enabling any fab to simply integrate a monolithic 3D device without changing the existing frontline fab process.

We were invited to join a panel session titled: "Monolithic 3D: Will it Happen and if so..." at IEEE 3D-Test Workshop. So we are happy to see monolithic 3D on the title, but then the title also suggests that the industry is wondering is it real or is it a pipe dream. The doubts are in opposition to companies such as Qualcomm who strongly advocate it, and the support CAE which Leti, in collaboration with STMicro and IBM, are presenting monolithic 3D as the "low-cost scaling" for 2018.

Monolithic 3D

The doubts might relate to the technology challenge illustrated by the following image.

Monolithic 3D

The IEEE S3S Conference 2015 in Sonoma, CA provided comprehensive coverage of R&D activities in the monolithic 3D space. It started with short courses on Monday. On Tuesday there was a planery talk "Sustaining the Silicon Revolution: From 3D Transistors to 3D Integration" by professor Tsu-Jae King Liu, followed by "3D-Invited Monolithic 3D Alternative Technologies" session with representives of Qualcomm, CEA Leti, Taiwan National Nano Device Laboratories, Stanford University and UCLA presenting and updating on the state of monolithic 3D technologies being developed around the world.

Monolithic 3D

On Wednesday, there was an additional session of "Invited Talks on M3DI" followed by a "Selected Papers on M3DI" session.

In short the most comprehensive technical event on the emerging monolithic 3D technologies.

Yet, the question "Monolithic 3D: Will it Happen..." was still being asked.

Monolithic 3D, yay or nay?

The concerns are that the leading edge vendors are too busy these days still with dimensional scaling and if anything else could be done it seems that FD-SOI would be it; while trailing edge fabs, are in most cases, avoiding any major transistor process development. The recent failure of Suvolta could be an indication of this reality.

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