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Impact of wearables, IoT on electronic design

Posted: 26 Oct 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Internet of Things? IoT? RAM? PCB layout? redistribution layer?

The market for the Internet of Things (IoT), which includes wearable electronics, smart homes, smart cars, smart TVs and smart machines, will exceed the personal computer, tablet and smartphone market combined by 2017 with a global installed base of 7.5 billion devices, according to an analysis by Business Insider. The 1990s fixed Internet wave and connected about one billion users; the 2000s mobile wave connected another two billion; Goldman Sachs estimates that the IoT has the potential to connect about 28 billion things, ranging from wristwatches to factory machinery, to the Internet by 2020.

One of the most exciting segments of the IoT market is wearables, which Business Insider estimates will grow at a rate of 35% over the next five years, reaching 148 million units annually by 2019.

Impact of IoT and wearables on electronic design
The unique characteristics of IoT and wearable products present some difficult design challenges. Today's IoT and wearables products must deliver ever-increasing capabilities in smaller packages with more aerodynamic shapes. For example, the Pebble Smartwatch is only 43 mm by 34 mm, or about one-fifth the area of a typical smartphone, and 10 mm thick. An LED display, memory PCB, SoC controller, several sensors, Bluetooth chip, and a battery are all mounted on a double-sided PCB within the Pebble's enclosure[4]. In addition to their smaller size, IoT and wearable products often require contoured form factors and flexibility to accommodate the shape and movement of the human body, which further complicates the design process. The increasing functionality and shrinking size of IoT and wearable products also obscures signal integrity and thermal management challenges.

Implementation of advanced technologies
The design challenge is also being complicated by increasing use of advanced packaging technologies to pack integrated circuits (ICs) more closely together in IoT and wearable products. Multichip modules (MCMs) are commonly used to achieve a small, thin form factor in smartwatches and smart glasses. System in Package (SiP) integration is being used to integrate digital logic, analog and RF subsystems into a single package. 3D-IC technology using through-silicon-vias (TSVs) is becoming common. Package-on-Package (PoP) structures are being used to leverage packaged RAM while still reducing interconnect distance. PCB technology has also evolved over the years with high density interconnect, flexible and semi-rigid PCBs, and embedded passive and active components on inner layers, inside cavities and within the dielectric of the board stack-up.

Shifting the focus from a board/package-level design to product-centric design
With small form factors becoming key to product success, more attention is focused on the critical early stages of the PCB and mechanical integration design process where requirements are translated to practical design decisions. A virtual prototyping process where cost, number of PCBs, weight, size, enclosure fit and more can be evaluated collaboratively with the ability to make trade-offs before committing to detailed design significantly lowers delivery risk. This is the stage where the product is configured and decisions such as how many boards are in the system and what functions are on each board are made. The new generation of design exploration tools provides a platform for concept and design creation through functional, 2D layout, 3D physical and BOM analysis views as well as preplanning board manufacturing aspects such as panel arrangement. Dynamic linking enables product planners to understand the impact of changes across every discipline involved in the design process.

Need for intelligent collaboration and co-design across disciplines
PCB layout and mechanical integration have become much more challenging, requiring greater collaboration than ever before between design disciplines. With mechanical engineers and board designers working with disconnected systems it's difficult to ensure physical compatibility. Traditionally, the PCB, package, IC and enclosures are each designed in their own stand-alone 2D environment. With increasing functionality, tight schedules, tighter cost constraints, and the decreasing form factor of today's IoT and wearable products, components need to be tightly coordinated with each other so that pin assignments can be optimized for small size and minimum layer count substrates. The overall goal is to align the boards, packages and chips so that signals follow the shortest possible path in the fewest layers possible from the chip through the board to the chip, resulting in the fewest possible layers across all substrates.

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