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Enabling functional safety in industrial apps

Posted: 29 Oct 2015 ?? ?Print Version ?Bookmark and Share

Keywords:automation? FPGA? programmable logic controllers? functional safety? finite state machines?

The increasing adoption of automation on the factory floor is a key driver for more processing bandwidth, integration of industrial-specific communications, and functional safety. The integration of FPGA devices into applications found on the factory floor, like programmable logic controllers (PLCs), industrial networking switches, and motor controllers is increasing due to their long lifetimes, high processing bandwidth, and flexibility to integrate many IP technologies. Due to the increasing adoption of automation technologies enabled by FPGA devices, which translates to greater interaction between people and machines, there is a need to integrate functional safety into FPGA-based products. To facilitate building functionally safe designs, robust synthesis tools that support defined methods are needed. One such tool is Synplify Premier, which provides FPGA designers with technologies that enable functional safety capabilities into their products.

The operation of FPGA-based products in harsh conditions ranging from high temperatures to high radiation environments can cause errors to be introduced. This creates a growing need to utilise special design techniques to detect in-system errors and to recover to correct operation. Synplify Premier provides designers with the ability to build-in these safety features to help mitigate errors and, ultimately, achieve greater design reliability.

The range of solutions enabled through Premier's design for high reliability capabilities include safe and fault tolerant finite state machines (FSMs), redundancy-based mitigation, support for I/O replication, memory error correction circuitry, and error monitors to trigger error correction. These capabilities can be used in any combination to suit the design. By utilising one of the redundancy-based mitigation strategies, a designer can create a circuit design that can be duplicated and compared.

Figure: Duplicate with compare example (Source: Synopsys).

Premier will automatically duplicate the circuit and add the compare circuitry with an error_flag output that can be tied to a local register accessible by the embedded software for system level control within the functional safety software stack. The embedded system software can read the error condition and respond with the correct recovery scheme.

In addition to redundancy techniques, designers need to take care with FSMs, which can become stuck in an invalid, and potentially disastrous, state. A soft error can force the state machine into an illegal state, so the tools must be capable of taking the original state machine representation as defined and augmenting it with the ability to detect and mitigate induced errors.

With today's small silicon geometries and higher reliance on "safe" designs, induced soft errors impose an increasing threat to reliable operation in multiple applicationsnot just in industrial environments, but also in things like automotive applications. By utilising redundancy, developing safe sequential logic, and creating fault-tolerant state machines with custom error mitigation logic, designers can protect their FPGA-based designs from soft errors.

As more applications require implementing functionally safe features, even at sea level, tools such as Synplify Premier become invaluable to designers.

About the author
Joe Mallett is a senior product marketing manager for FPGA-based synthesis software tools at Synopsys. He has 20 years of experience in design and implementation within the semiconductor and EDA industries. Before joining Synopsys, Joe was a senior product marketing manager at Xilinx Semiconductor where he worked to define and launch FPGA products. His background includes SoC design/prototyping, embedded software, HDL Synthesis, IP, and Product/Segment Marketing. He holds a BSEE from Portland State University.

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