Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Memory/Storage
?
?
Memory/Storage??

Flash storage: 3D TLC NAND to beat MLC (Part 2)

Posted: 30 Oct 2015 ?? ?Print Version ?Bookmark and Share

Keywords:solid state drives? SSDs? Single-Level Cell? NAND? Multi-Level Cell?

In the previous instalment, we discussed the advantages and challenges associated with solid state drives (SSDs). The need to reduce cost, as well as increase density, has taken the industry to 10nm-class NAND geometries that are reaching a physical limit in how densely memory cells are packed together. In this segment, we discuss alternate methods to increase density, as well as how a new innovation addresses SSD challenges surprisingly well.

Increasing density via multi-bit cells
An orthogonal approach to geometry shrinks for accommodating increased density is to increase the number of bits per cell. The industry started with what is called SLC (Single-Level Cell) NAND, which holds one bit of information per cell. To increase density, MLC (Multi-Level Cell) NAND was developed that holds two bits of information per cell. Because of the need to now distinguish between 4 voltage levels instead of 2, the cell is more sensitive to physical degradation and as a result, has lower endurance compared to SLC NAND. For example, SLC NAND can withstand approximately 70K P/E (Program/Erase) cycles before a cell fails. In comparison, MLC NAND endurance is in the 18K P/E range. However, using sophisticated algorithms mentioned above (wear-leveling, bad block management, ECC), SSD vendors are able to mask much of the reduction in NAND P/E cycles at the drive level.

Figure 1: Storing Data in SLC, MLC, and TLC NAND.

Another technique, known as Over-Provisioning (OP), can also be used to increase drive endurance. OP sets aside a minimum amount of free space which is inaccessible by the user or Operating System (OS), where the SSD controller can use as "swap space." An SSD is always moving data around to ensure even wear of the drive. The ratio of "drive writes" to actual writes instructed by the host is called the Write Amplification Factor (WAF). Having this extra space reduces the WAF, hence improving drive endurance.

In the past, only SLC NAND was widely considered for enterprise applications. But with the sophisticated techniques available to vendors, SSDs with endurance levels of up to 25 DWPD (drive writes per day, for 5 years) are possible using MLC NAND. Customers are still becoming familiarized with how many DWPD are needed to support what are considered write-intensive, mixed-use, and read-intensive applications. Current trends suggest that the DWPD requirements are converging into three main "swim-lanes": 10DWPD, 3 DWPD, and Introducing 3D TLC NAND
Because of the need to continue down an aggressive cost-curve, TLC (Triple-Level Cell) NAND-based SSDs were introduced in 2012. TLC NAND holds 3bits of information per cell. This means there is a need to distinguish between 8Vage levels to decipher the information held, and as such, endurance is reduced even further. The P/E cycle of planar TLC NAND is in the 1K range, and the technology was met with the same scepticism that faced MLC NAND when it was first introduced in SSDs back in 2008.

At the same time, it was apparent that the NAND industry needed a breakthrough in order to continue down its aggressive cost curve. A physical limit was being reached in terms of being able to shrink the geometry further (inter-cell interference, as well as the reduced number of cells available to hold charge). This is where Samsung led the industry by introducing 3D NAND. With 3D NAND, instead of further squeezing cells closer together, the 3D CTF (Charge Trap Flash) cells are stacked vertically on top of each other to increase density. This is a paradigm shift in terms of scaling density and cell structure, and is what will best allow the industry to continue along the cost efficiency curve.

A key benefit of 3D NAND technology is that it can use a larger process geometry and still get better densities than planar NAND. Larger memory cells have the benefit of yielding faster, more reliable NAND. It also consumes less power, related to the time required to program the flash. 3D NAND is what allows TLC to perform at levels comparable to planar MLC.

Figure 2: Cell-to-cell Interference Mitigated by 3D NAND.


1???2?Next Page?Last Page



Article Comments - Flash storage: 3D TLC NAND to beat M...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top