MIPI D-PHY IP works at 2.5Gb/s per Lane on TSMC 16nm FinFET+

Synopsys Inc. has showcased MIPI D-PHY IP on TSMC's 16nm FinFET Plus (16FF+) process operating at 2.5Gb/s per lane. The demonstration shows the DesignWare D-PHY receiver (Rx) lane connected to Keysight Technologies' test equipment, which provided burst-mode stimulus for stressed eye testing and the transmitter (Tx) lane connected to the Keysight oscilloscope displaying the transmitter's performance.

The DesignWare MIPI D-PHY operating at very high speeds on the 16FF+ process, enables designers to meet their power and performance requirements while ensuring interoperability with the latest image sensors and displays. Synopsys' silicon-proven D-PHY IP is compliant with the MIPI D-PHY v1.2 specification and delivers 50 per cent lower power and smaller area compared to other competitive solutions, stated the company.

Synopsys' DesignWare MIPI D-PHY, CSI-2 and DSI IP are available in a variety of advanced processes. The verification IP for these interfaces is also available.