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Synopsys flaunts massive deployment of IC Compiler II

Posted: 28 Oct 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? IC Compiler? process node? infrastructure? design?

Synopsys Inc. has revealed that its IC Compiler II place and route system has been deployed on more than 100 production designs in the first year since its release in 2014. This usage includes more than 50 unique customers across 18 different foundry process nodes.

According to the company, this successor to IC Compiler has enabled first-pass silicon success on dozens of these production designs ranging from 130nm to the latest 10nm process node. Throughout its broad, real-world usage, IC Compiler II has consistently demonstrated a ten-fold improvement in throughput while achieving even higher quality of results (QoR), boasted Synopsys. Industry leaders pursuing advanced applications have successfully deployed this place and route system on IP blocks at the chip level, while others have completed multiple tapeouts. Many have even chosen to displace incumbent third-party solutions.

IC Compiler II promises to deliver the highest productivity and best QoR for designs across all process nodes. Architected around a modern, low-memory footprint and natively multi-threaded infrastructure, IC Compiler II is able to handle designs comprising more than 500 million placeable instances hierarchically, and has proven capacity for over 10-million instance block implementation.

Comprised of an optimised, place and route-focused data model, coupled with an extensible library system offering unique, geographically separated development capabilities, IC Compiler II eases user adoption by using industry-standard input and output formats, as well as familiar interfaces and process technology files.

Additionally, IC Compiler II brings industry-leading, ultra-high-capacity automated design planning, unique clock-building technology and patented global analytical optimisation that result in a highly convergent design implementation flow. Together, these technologies enable enhanced QoR across all key power, performance and area implementation metrics as well as accelerate that all important time-to-market goal.

The culmination of numerous years of engineering innovation, these industry-first technologies enable IC Compiler II to deliver 5X faster runtime along within half the memory footprint while requiring half the iterations required to achieve the same target QoR, ultimately resulting in a 10X boost in design throughput and designer productivity.





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