Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > FPGAs/PLDs
?
?
FPGAs/PLDs??

Examining metal eFuses

Posted: 16 Nov 2015 ?? ?Print Version ?Bookmark and Share

Keywords:eFuses? Intel? processor? Westmere/Clarkerdale? TSMC?

This yields an approximately 170 oC temperature rise for the middle portion of the fuse, which is not hot enough to accelerate the electromigration process by a meaningful amount.

Our assumption for constant resistivity in equation (2) is clearly wrong as metals exhibit a positive temperature coefficient for their resistivity given by

Where a is the temperature coefficient for Cu (3.9 x 10-3 K-1). Inserting the 170 oC temperature rise from (2) into (3) shows the resistivity of the middle portion of the fuse to increase by nearly 70%. This increased resistance in the middle of the fusible link results in an accelerated Joule-heating (IR heating), leading to thermal runaway. We think this thermal runaway plays a dominant role in the TSMC fusing action and not electromigration.

Now TSMC, in their US 8,749,020 ('020) patent, is suggesting that they are forcing the fusible link to preferentially fuse in the middle portion by exploiting chemical-mechanical polishing (CMP) microloading effects to thin the middle portion of the fuse, thereby increasing its resistivity. The '020 patent suggests that the thickness of the fusible link is influenced by the presence of adjacent dummy metal patterns, where large adjacent dummy metal patterns result in an increased rate of metal removal from the fusible link during CMP. This, they argue, results in the middle portion of the fuse being thinner than the end pieces as seen in below.

Figure 5: Schematic fuse cross section (USP 8,749,020)

But the dummy metal 2 stripes seen in figure 4 seem to be too small to influence the CMP processing of the fusible link. The image below is a SEM cross section taken along the length of the TSMC fuse through its end pieces but it is not quite into the fuse itself.

Figure 6: SEM cross section TSMC fuse. We are not convinced that the middle portion of the fuse is thinned relative to the ends.

Source: Qualcomm Gobi MDM9235 Modem 20 nm HKMG Logic Detailed Structural Analysis, TechInsights

Furthermore, our TEM cross section, figure 7, of some dense pitch and an isolated metal 3 lines suggests that local patterns of metal do not influence the metal line width nor its thickness.

Figure 7: Minimum pitch metal 3 TSMC 20 nm process (Source: Qualcomm Gobi MDM9235 Modem 20 nm HKMG Logic Detailed Structural Analysis, TechInsights)

We are suggesting that TSMC's dummy metal stripes are not being used to shape the fusible link, but rather serve as barriers to material being ejected from the blown fuse. And, IBM's eFuse patent (8,421,186) supports this explanation. The '186 patent suggests that the dummy metal stripes, which they describe as blocking lines, serve as barriers to the ejected debris from the blown fuse.

The term 'ejected debris' suggests a violent fusing process, much like what we see with Intel's fuse (figure 2). If so, TSMC's dummy metal 2 stripes are likely being used as barriers to keep the ejected copper from diffusing into adjacent circuitry.

So after much reverse engineering effort, we think we understand how these eFuses work.

About the authors
Kevin Gibb is Product Line Manager at TechInsights.

This piece was co-authored by Lev Klibanov, process analyst at TechInsights. Klibanov has more than 10 years of semiconductor process development and also specializes in device physics, process optimization and simulation, and semiconductor reverse engineering.


?First Page?Previous Page 1???2???3



Article Comments - Examining metal eFuses
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top