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Get 500W in converter with GaN (Part 2)

Posted: 14 Dec 2015 ?? ?Print Version ?Bookmark and Share

Keywords:eGaN FETs? MOSFETs?

In Part 1 of this series, we discussed the advantages of eGaN FETs, and showed how these translated directly into better efficiency and vastly improved power density via the example of a 500W eighth-brick demonstration converter. This is a 70% increase in power over the best silicon has to offer. We further showed that for an unregulated design, we could achieve an astounding 667W. eGaN FETs are the key to making this possible, but to get this kind of performance, an engineer has to think carefully about the design of the converter. With silicon MOSFETs, the reduced performance of the FETs overshadowed much of these details. However, once the designer dives in and gets into the proper mindset, it will pay many dividends.

In Part 2 of this article, we dive into some of the key details of physical and electrical design. We will look at layout, key waveforms, and losses. Along the way, one may notice things that could be improved. We summarise key potential improvements near the end of the article.

In order to get the maximum benefit from using eGaN FETs, proper attention to layout is crucial. Our approach is to do the entire power stage first, including gate drives and bus caps, and make everything else work around it. This approach is not unique to working with GaN, but the performance compromises with silicon and its complex packaging can obscure much of the benefit of a good layout. The key points in the layout are:
???Minimise power loop inductance to minimise losses and ringing [1].
???Maximise power stage symmetry in order to maximise volt-second balance on the transformer [2].
???Use copper for thermal management wherever it does not compromise electrical performance.
???Do not let power currents flow across signal grounds.

For reference, we show again the simplified schematic of the converter in figure 1.

Figure 1: Simplified schematic of E-brick converter.

The PCB is implemented with a 12 layer board. The ten inner layers are 4 oz. (140?m) copper to handle the high currents, and the outer layers are 2 oz. (70?m) to accommodate the finer pitch of the surface mount components. The board uses 3 types of vias: through vias, buried vias (layers 2-11), and microvias (layers 1-2 and 11-12). All vias are filled and plated to allow via-in-pad design with reliable soldering. The microvias provide a low electrical and thermal resistance for the FETs, and greatly simplify the remaining layout.

Figure 2 shows a top-down view of the overall layout. We see the full-bridge input on the left, which feeds the integrated planar transformer windings, and finally the synchronous rectifiers (SRs). The snubbers are adjacent to each SR. The controls take most of the remaining space. The bottom side contains the input and output filter inductors, the bias supply, and the signal isolation. Finally, we note the line of symmetry for the power stage. Small variations are acceptable, but this symmetry is important to maintain volt-second balance on the transformer without the need for a blocking capacitor or primary side current sensing.

Figure 2: Overview of converter layout (top view).

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