Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > T&M

PCIe clock jitter measurement tool streamlines timing design

Posted: 08 Dec 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Silicon Labs? timing design? PCIe? clock jitter? FPGA?

Silicon Labs has uncloaked a free software tool that allows engineers to rapidly and easily measure PCI Express (PCIe) clock jitter from an oscilloscope data file in just a few simple clicks, making it easy to verify PCIe specification compliance and reduce system development time. Silicon Labs' clock jitter tool is the first standardised jitter calculator readily available for the PCIe 1.0, 2.0, 3.0 and 4.0 specifications, at no charge, to anyone developing applications based on the PCIe architecture. Designed to support PCIe common clock and separate clock architectures, the tool is open to the industry and not restricted for use with Silicon Labs' clock products.

Silicon Labs' jitter measurement tool for PCIe technology is available to developers now and can be downloaded free of charge at

Since its inception as a serial interconnect for desktop PCs more than a decade ago, the PCIe standard has evolved over three generations to become widely deployed in blade servers, storage, embedded computing, IP gateways, industrial systems and consumer electronics. PCIe technology has also been adopted for FPGA and SoC devices to provide a versatile, high-performance means of transferring data within systems. While the PCIe specification specifies a 100MHz reference clock with ±300ppm frequency stability, some FPGA and SoC designs may operate internally up to 250MHz, making clock jitter evaluation a critical design consideration.

Filter masks and jitter calculations for PCIe technology are often misunderstood during the development process. Most oscilloscopes are not equipped with the necessary filter masks to enable correct PCIe clock jitter measurements, which can lead to confusion regarding why a measured result does not match data sheet specifications. Developers often report PCIe jitter measurements higher than clock data sheet specifications, indicating incorrect measurements rather than design issues. Silicon Labs created the PCIe jitter tool to address these needs, providing hardware designers with a downloadable utility that quickly determines if the measured clock meets PCIe jitter requirements.

Silicon Labs' clock jitter tool for PCIe technology features an intuitive graphical user interface that guides developers through the few simple steps required to compute clock jitter from an oscilloscope data file. The tool includes all filter masks defined by the PCI-SIG for PCIe 1.0, 2.0, 3.0 and 4.0 common clock and separate reference clock architectures, supporting both independent spread spectrum (SRIS) and non-spread spectrum (SRNS) technologies. The jitter results are displayed in a concise, easy-to-read summary format that takes the guesswork out of ensuring the system design meets PCIe specifications with sufficient jitter margin. For added convenience, the jitter measurements can be saved as a PDF file for future reference.

Article Comments - PCIe clock jitter measurement tool s...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top