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Imec showcases next-gen devices to supersede silicon

Posted: 14 Dec 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Imec? silicon? FinFET? CMOS? spintronics?

During the recent IEEE IEDM conference, Imec has revealed record enhancement of novel InGaAs Gate-All-Around (GAA) channel devices integrated on 300mm silicon. The nano-electronics research centre also looked into emerging tunnel devices based on optimisation of the same III-V compound semiconductor.

III-V-on-Si GAA devices with a record peak transconductance at 0.5V has been achieved by optimising both the channel epitaxy quality and the gate-channel passivation. In search of device technologies beyond FinFETs and GAA-nanowires for sub-0.5V operations, Imec investigates InGaAs Tunnel-FET (TFETs). Homo-junction III-V TFETs achieving a record ON-state current (ION) and superior subthreshold swing have been demonstrated. These results increase the knowledge on the impact of defectivity and channel optimisation on device operations, and pave the way to advanced logic devices based on III-V-On-Si for high performance or ultra-low power applications.

Imec's R&D programme on advanced logic scaling is targeting the latest and mounting challenges for performance, power, cost and density scaling for future process technologies. One of the directions that Imec is following, looks into beyond-Si solutions, such as integrating high-mobility materials into the channels of CMOS devices to increase their performance, and the integration challenges of these materials with silicon. Gate-All-Around Nanowire (GAA NW) FETs have been proven to offer significantly better short-channel electrostatics, and quantum-well FinFETs (with SiGe, Ge, or III-V channels) achieving high carrier mobility, are interesting concepts to increase device performance. Tunnel FETs, on the other hand, offering a steeper than 60mV/dec subthreshold swing, are a promising option for ultra-low power applications.

InGaAs Nanowire FET and HRTEM

TEM of complete gate-all-around InGaAs Nanowire FET and HRTEM of the gatestack

At IEDM, Imec presented gate-all-around InGaAs Nanowire FETs (Lg=50nm) that performed at an average peak transconductance (gm) of 2200?S/?m with a SSSAT of 110mV/dec. Imec succeeded in increasing the performance by gate stack engineering using a novel gate stack ALD inter-layer (IL) material developed by ASM, and high pressure annealing. The novel IL/HfO2 stack achieved a 2.2 times higher gm for a device with a gate length (Lg) of 50nm, compared to the reference Al2O3/HfO2 stack.

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