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Grasp soft-decoding in SSD controllers

Posted: 23 Dec 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Low-Density Parity-Check? LDPC? Solid-State Drive? SSD? NAND flash?

Some examples of a Re-Read Strategy might include:

1. Read the same section as the original hard data but use a different set of read threshold voltages inside the NAND.

2. In MLC NAND, read the section that shares the same word-line as the original section.

3. Read the section that corresponds to the dominant disturber. This is the section that, when programmed, has the strongest program disturb impact on the original hard-data section.

There are pros and cons to each of these Re-Read Strategies and, in fact, the three can even be combined together if desired. Just remember that each time you read from the flash you will incur more latency!

The soft-data construction: Each of the reads in our Re-Read strategy returns the 0 and 1 data associated with that read. Although slightly more advanced multi-bit reads might exist in more advanced NAND, we will ignore that for the purposes of this article. Therefore each read of the flash gives us one more bit of physical information. However we need to map these physical zeros and ones into soft information for the LDPC decode. This mapping requires an understanding of both the NAND flash and the LDPC codes that are being used.

Here's a very simple example to illustrate: For a hard-data decode we can use a very simple mapping to convert the zeros and ones from the flash into information the LDPC decoder can consume. We call the output of this mapping Log-Likelihood Ratios (LLRs). This mapping is given in table 2.

Table 2: The mapping from NAND Flash value to LLR for a simple hard-data decode.

Now assume our Re-Read strategy consists of one additional read. Our soft-data construction might look something like as shown in table 3.

Table 3: The soft-data construction table for a simple example involving two reads of the NAND Flash device.

The soft LDPC decode: The final step in the soft-data decode involves passing the LLRs for each of the bits of the codeword into the LDPC decoder logic. The hope is that this decode will be more successful than the original hard-data decode was and the SSD will now be able to return the user data and perhaps move that data to a safer region of the SSD so that it can be recovered more easily the next time it is requested.

Given the characteristics of the latest generation of NAND technology, LDPC engines will be required to meet an acceptable bit error rate. We've seen there are side-effects of using LDPC, and leading controllers that utilise the latest LDPC technologies and algorithms will be able to more effectively extract commercial value from the NAND devices they manage.

About the author
Stephen Bates is a senior technical director in the Chief Strategy and Technology Office of PMC-Sierra. He works on issues related to NAND flash and other Non-Volatile Memory technologies and the implications of those technologies on storage architectures. He holds a PhD from the University of Edinburgh and is a Senior Member of the IEEE.


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