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TSMC begins work at 5nm, plans for EUV remain unclear

Posted: 17 Dec 2015 ?? ?Print Version ?Bookmark and Share

Keywords:TSMC? EUV? immersion lithography? ASML? 193i?

Taiwan Semiconductor Manufacturing Co. has revealed that it has begun work on a 5nm process to push ahead its most advanced technology, yet the company is still undecided on the adoption of extreme ultraviolet lithography (EUV) at that node. The world's largest foundry, which hasn't yet put 5nm on its product roadmap, is still mulling whether to use EUV lithography as part of the process.

Mark Liu, TSMC co-CEO, made the comments about the company's 5nm work at a supply chain management conference in Hsinchu, Taiwan earlier this month.

TSMC's initial development work at 5nm may be yet another indication that EUV has been set back as an eventual replacement for immersion lithography. ASML Holding has been a key proponent of EUV, while competitor Nikon is backing 193i immersion technology.

Tests continue to indicate that a combination of 193-immersion and EUV may be the best solution for the 5nm node as the semiconductor industry pushes the limits of Moore's Law. TSMC has noted details of its 10nm process that will require triple patterning.

A 193i-only approach is potentially the most expensive, requiring quad patterning for metal layers and triple patterning for vias. An all-EUV approach needs fewer layers and supported better area, power and performance but it is not practical given the still immature state of EUV systems.

The extension of 193nm immersion to 7nm and beyond is possible, yet it would require octuple patterning and other steps that would increase production costs. It could become a speed bump for chipmakers planning to adopt finer geometries, slowing the growth of the chip industry.

IBM Research earlier this year beat Intel to the 7nm node by perfecting EUV lithography and using silicon-germanium channels for its finned field-effect transistors (FinFETs). That helps IBM development partner Samsung in a race to catch up with Intel by 2018 when the first 7nm products are expected.

In October this year, TSMC said it has produced fully functional SRAMs at the 7nm node, and it expects initial production at 7nm in 2017. The company will begin technology qualification for 10nm during 4Q15, and customer tapeouts will start early in 2016. In September this year, the company reported progress with EUV systems running at 90W and expectations to have throughput as high as 125 wafers/hour later this year.

- Alan Patterson
??EE Times





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