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Enhance test quality, minimise DFT costs

Posted: 05 Jan 2016 ?? ?Print Version ?Bookmark and Share

Keywords:Logic BIST? IP? Tessent TestKompress? Cell-Aware? DFT?

Mentor Graphics' hybrid silicon test solution merges the two prominent logic test methodologiesembedded deterministic test, the technology behind Tessent TestKompress, and logic built-in self-test (Logic BIST)into a single test IP, as shown in the figure.

As someone familiar with both technologies, I wasn't surprised that we found a way of merging the hardware implementation into a single IP, which saves up to 30% area for the controller alone. The more interesting question is why it was done. OK, 30% reduction is always good to have, but how many designs actually need both test solutions simultaneously? I found the answer to my why question when I figured out who would need such a hybrid IP.

Let's start with embedded compression ATPG (TestKompress). Embedded compression has been around for more than 10 years. It lets the test engineer add more test patterns into a given pattern volume on the tester (ATE). With these additional patterns, the test engineer can achieve higher quality production tests.

There have been recent advances in ATPG that improve the quality of test, such as the newer Cell-Aware test patterns. Who is using this form of testing? Everyone who has either a large design or requires high test quality.

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Figure: Embedded data compression lets you increase the number of test patterns that ATE can run.

What can logic BIST add to this? Not much, really. If you want to achieve about the same test quality as you do with TestKompress, you have to invest heavily in testability enhancements, like adding many control and observe points to keep your design free of x-sources. In general, the costs for an equally high-quality logic BIST solution become prohibitiveand very quickly. But this thinking assumes someone would want to use logic BIST in lieu of TestKompress in production testing. In general, though, this is not how logic BIST is used.

The primary user of logic BIST needs an in-field or in-system test system that can be activated at any time. Designs in the automotive industry are a good example. As an example, at every power-up, the electronics in the braking system go through a self-test loop. You can easily imagine that there are many more systems you want to know will actually work when you need them.

To achieve the quality requirements being driven by standards such as ISO 26262, the automotive industry aims at zero DPM (defects per million) of shipped parts. In addition, these parts need to have in-system self-test capabilities. The former requirement is usually achieved by extremely high-quality test patterns, the latter by using logic BIST.

It is those users who are implementing both TestKompress and logic BIST into the same design. Following this line, I can imagine that other industries with similarly high-quality requirements and in-system test needs would also implement both. Aerospace and military systems come to mind, but what about medical devices and systems that can't easily be serviced?

By having both test solutions implemented, you can exploit additional advantages of this hybrid solution. I mentioned that logic BIST for production test is not desirable if you want the highest quality. But, nothing prevents you from using logic BIST for finding the easy defects, which provides up to 80% or 90% coverage. This doesn't cost much in terms of DFT investments, but it leaves even more pattern volume for TestKompress to target tests for the tough-to-detect defects. The combination achieves even higher quality levels than either method alone.

About the author
Martin Keim received the Ph.D. degree in informatics from the Albert-Ludwigs University of Freiburg, Freiburg im Breisgau, Germany. He joined the Silicon Test Solutions Group of Mentor Graphics, Wilsonville, OR, USA, in 2001, where he is currently the Engineering Manager of the Memory Built-In Self-Test team. He is an active member of the IEEE 1687 Working Group and was an Editor of the sixth edition of the Microelectronics Failure Analysis Desk Reference Manual, responsible for the test and diagnosis chapters. He also holds several national and international patents and has authored numerous technical publications. He has served for many years on the organising committee of the International Symposium for Testing and Failure Analysis, for which he will be the General Chair in 2016.





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