Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Minimising risk through hardware emulation

Posted: 30 Dec 2015 ?? ?Print Version ?Bookmark and Share

Keywords:hardware emulation? risk? RTL? debugging? processor?

Risk aversion, which comes from the uncertainty associated with committing a design to silicon, is the name of the game.

December is normally a month in which we take a moment to look back over the preceding year. With this in mind, I skimmed through the blog posts I've written for EE Times in 2015 on one of my favourite topics: hardware emulation. What struck me as an unwritten, but recurring, theme is hardware emulation's ability to alleviate risk for development teams and project managers.

I can think of an analogy to buying an insurance policy. Such a policy may protect you and your family against the risk of a premature death, a house disaster, a car crash and other unforeseen calamitous events. Likewise, hardware emulation provides insurance to reduce, or eliminate, costly re-spins. And, even more important, hardware emulation can accelerate time-to-market by delivering thoroughly verified RTL and gate-level designs to the backend design flow, along with validated embedded software ahead of silicon availability. Furthermore, it can perform post-silicon testing to weed out any bugs remaining after tape-out.

"Why and how is all this possible?" you may wonder.

Hardware emulation is the most versatile verification tool ever developed, and now it has gone mainstream. It has the speed, performance and capacity necessary to tackle even the most complicated debugging scenarios that often include embedded software content. Bugs hiding out in the most complex chips designed today, such processors, graphics engines, or networking switches and routers, have now met their match with hardware emulation.

During a panel session at an industry conference earlier this year, a verification engineer was asked what he used emulation for. His reply: "Everything!" It's a safe bet he knows that much of the risk associated with debugging a chip has been removed through his hardware emulation resource.

In my travels to India, Europe and throughout the US this year, I heard many times that hardware emulation is a highly-valued and well-used verification tool. As I wrote in January, its four deployment modes and (at that time) at least eight verification objectives could be why. All of them concur to alleviate risk. No project team wants to chance failure by committing a buggy chip to silicon and enduring an expensive re-spin.

1???2?Next Page?Last Page



Article Comments - Minimising risk through hardware emu...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top