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A tech walkthrough of metal gate I/O transistors

Posted: 19 Jan 2016 ?? ?Print Version ?Bookmark and Share

Keywords:CMOS? transistors? SoC? I/O? NMOS?

There are a number of materials written about metal gate CMOS transistors for low-voltage applications such as processors and system on chip (SoC) devices. But these devices are connected to the outside world and require input/output (I/O) transistors that support higher bias voltages. Little is said about input/output (I/O) transistors. We at TechInsights think that they are worth a look.

We begin with a polysilicon gate I/O transistor, in this case from a 28nm node MediaTek part fabbed by TSMC (figure 1). The I/O transistor has a fairly long gate length (160nm) that is typical of I/O transistors. This long gate length reduces the magnitude of the lateral electric field in the channel region beneath the gate. We care about this lateral field as it gives rise to hot carrier injection of electrons (NMOS) or holes (PMOS) from the channel into the gate dielectric that can degrade the transistor's electrical performance.

The term hot carrier, refers to electrons and holes having lots of kinetic energy that is picked up from the lateral electric field in the channel, as they traverse from the source to drain. These energetic carriers can be injected from the channel into the gate dielectric due to the vertical electric field under the gate. This degrades the transistor performance by shifting its threshold voltage, altering its sub-threshold swing, and usually reducing the on-state drive current, ION; all bad things that need to be avoided.

The MediaTek transistor (shown in figure 1) has been delineated with a glass etch, that has done a good job of showing the dielectrics and metallisation, but does not really show the source and drain implants. We have outlined where we think they are, and these correspond to the slightly etched portions of the silicon substrate under the source and drain contacts.

The upper surface of the source diffusion is covered by nickel silicide as is part of the gate and the heavily doped drain region. The silicide is used to reduce the series resistance of the source/drain and gate layers.

The drain diffusion includes a drain extension with no overlying NiSi, as does the one end of the polysilicon gate. Several process generations ago, this drain extension would have been lightly doped, and called a lightly doped drain (LDD), but they are more heavily doped now and are just called drain extensions. They are still less heavily doped than the source/drain contact regions and this is done to improve their avalanche breakdown characteristics.

Figure 1: TSMC 28nm Node Poly Gate I/O Transistor (Source: Logic Detailed Structural Analysis of the MediaTek MT6589 Quad-Core System-on-Chip (SOC), TechInsights)

The 28nm node is perhaps the last logic process node to use polysilicon gates, and most advanced CMOS processes are now using metal gates with a metal oxide/oxide gate dielectric (typically HfO2/oxide). Intel was the first to adopt metal gate (HKMG) transistors at its 45nm node in 2009, but we continue our story with their 32nm SoC introduced in 2012.

We choose the 32nm process, as Intel revealed some of its 32nm HKMG process technology in their 2009 IEDM paper, including their 1.8 V I/O transistor. Here, Intel disclosed that the I/O transistor shares the same gate metallisation as the core logic transistor, but has a thicker gate dielectric and somewhat longer source/drain regions.

We show Intel's 32nm I/O transistor in figure 2 along with a logic transistor (inset). And we do indeed see a thicker gate dielectric (1.9 nm thick HfO2 and 3nm thick oxide). The NMOS core logic transistors, in contrast, have an approximately 1.2nm thick HfO2 and 0.9nm thick oxide layer thicknesses, respectively.

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