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Exploring Samsung's 14 nm LPE FinFET

Posted: 03 Feb 2016 ?? ?Print Version ?Bookmark and Share

Keywords:Samsung? Exynos 8? finFET? transistor? NMOS?

There has been some buzz on Samsung's Exynos 8 SoC as the company prepares to launch its 14 nm Low Power Plus (LPP) process, which is an update to its current Low Power Early (LPE) process used in its Exynos 7 SoC and the Apple A9 SoC.

There are now three foundries capable of making finFET transistors: Intel, Samsung and TSMC. Now, there is talk of Samsung's updated 14 nm LPP finFET process. We won't know the details of this process until we get our hands on some samples of either Samsung's Exynos 8890 SoC, or Qualcomm's Snapdragon 820 SoC later this spring, but we can reveal more of the 14 nm LPE process technology used in the Exynos 7420.

We begin with a tilt view SEM image of a typical Samsung 14 nm LPE finFET transistor in figure 1. The transistor channels are formed as silicon fins than run from the lower left to the upper right of the photograph. The fins are buried under dielectrics and are not visible, so we have drawn arrows to indicate their orientation. The metal gates lie in the orthogonal direction, wrapping over the sides and tops of the fins. Large source and drain (S/D) contacts are seen on either side of the gate electrodes.

Figure 1: Tilt view SEM image of Samsung 14 nm FinFET transistors (Source: Samsung 14 nm Exynos 7 7420 Logic Detailed Structural Analysis, TechInsights)

The layout of the gate and fins is perhaps more clearly seen in figure 2 of another set of Samsung finFET transistors, which is a plan view SEM image of a few FinFET transistors. Four silicon fins are aligned in a vertical direction, underneath the metal gates that run in the horizontal direction. The two transistor structures are surrounded by a well contact ring, that serves to isolate them from the rest of the circuitry on the die.

The fins have a 49 nm pitch that require a double patterning process to make them. There are two choices: litho-etch litho-etch (LELE) that Intel is believed to be using, or self-aligned double patterning (SADP). We think Samsung is using the LELE process to pattern these fins. An additional mask and litho process is required to cut the ends of the transistors.

Figure 3: TEM cross section of a typical NMOS transistor used by the Exynos 7420 (Source: Samsung 14 nm Exynos 7 7420 Logic Detailed Structural Analysis, TechInsights)

Figure 3 is a TEM cross section of a typical NMOS transistor used by the Exynos 7420, and we note that the roughly 30 nm measured gate length is nowhere close to the claimed 14 nm process node and this is true for both Intel and TSMC as outlined in Table 1. We will discuss this later.

The transistor gates are fabricated using a replacement gate process. This involves depositing a sacrificial layer, typically polysilicon, patterning and etching to form approximately 30 wide stripes. These stripes will define the transistor gate lengths.

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