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IP subsystem speeds up data fusion processing in IoT apps

Posted: 02 Feb 2016 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? IP subsystem? IoT? processor? DSP?

Synopsys Inc. has revealed what it describes as an integrated, pre-verified hardware and software IP product optimised for highly efficient DSP performance and ultra-low energy consumption. The DesignWare Smart Data Fusion IP subsystem provides a choice of DesignWare ARC EM DSP processors, including the latest EM9D and EM11D cores with support for XY memory to boost signal processing performance.

An integrated microDMA controller cuts system-level energy consumption by enabling data transfers while the processor is in one of several programmable sleep modes. The integrated peripherals, memories, hardware accelerators and software DSP functions deliver the performance efficiency needed for common processing tasks in Internet of Things (IoT) applications such as always-on sensor fusion, voice and image detection and audio playback.

The DesignWare Smart Data Fusion IP subsystem is geared to process data from numerous digital and analogue sensors with minimal power consumption, offloading the host processor and enabling more efficient processing of sensor data, according to the company.

The fully configurable IP subsystem includes an ARC EM5D, EM7D, EM9D or EM11D processor. This family of power-efficient cores combines RISC and DSP processing and includes support for XY memory banks to enable a sustained throughput of one 32x32 MAC operation (or two 16x16 MAC operations) per clock cycle. The additional signal processing bandwidth is optimised to manage the extensive data processing required by advanced sensor fusion algorithms and to improve processing efficiency for a range of audio formats including MP3, SBC, OPUS and AAC LC. For example, executing codecs such as Bluetooth Low Complexity Sub-band Coding (SBC) with ARC processors requires less than 40?W in 40nm low-power processes with frequency (MHz) requirements more than 25 per cent lower than competitive processor offerings, the company added.

DesignWare Smart Data Fusion IP subsystem

DesignWare Smart Data Fusion IP subsystem integrated hardware and software solution

The subsystem's integrated microDMA controller enables memory and peripheral access during processor sleep modes and provides 4X faster access times compared to traditional bus-based DMA implementations, noted Synopsys. In addition, the subsystem incorporates highly-optimised I/O peripherals including multiple SPI, I2C and analogue-to-digital converter interfaces, further lowering gate count and energy consumption while reducing engineering effort.

To ease software development, the subsystem includes software drivers and a rich library of off-the-shelf DSP functions supporting filtering, correlation, matrix/vector, decimation/interpolation and complex math operations. Designers can implement these sensor-specific DSP functions in hardware using a combination of native DSP processor instructions and tightly coupled hardware accelerators to boost performance efficiency and reduce power consumption. The subsystem is supported by commercially available software covering a range of IoT functionality, including speech recognition, voice control, motion sensing and audio post-processing and playback. Additionally, Synopsys' embARC Open Software Platform gives software developers online access to a comprehensive suite of free and open-source software that accelerates code development for the subsystem.

The DesignWare Smart Data Fusion IP subsystem will be available in February 2016.

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