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Intel exec sees huge potential for Moore's Law post-CMOS

Posted: 03 Feb 2016 ?? ?Print Version ?Bookmark and Share

Keywords:Intel? CMOS? Moore's Law? transistor? FET?

"It's too early to make a prediction on the details of the 7nm node, but we can say we may be more in the range of the historical line of cost per transistor reduction at 7nm, but we see a feasible path to cost reduction," he said.

After his talk, Holt clarified that predictions of Intel's 7nm node fall in a range extending from the historical cost/transistor reductions to the slight improvements Intel reaped at 22nm and 14nm. "Lots of things are still up in the air, so we don't know where we will fall in that window," he added.

Intel has not given up hope it may be able to start using extreme ultraviolet lithography sometime after 7nm production begins. EUV could have a significant impact on 7nm costs, reducing the need for multi-patterning.

Separately, Holt noted Intel's 10nm process will support five voltage threshold levels. The variety of optimisation points in a given node will likely increase as post-CMOS technologies are added to the mix.

Intel's upcoming 10nm process

Power options are increasing, said Holt, noting the low power version of Intel's upcoming 10nm process will support five voltage thresholds.

- Rick Merritt
??EE Times


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