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Isolated potentiometer design (Part 2)

Posted: 22 Feb 2016 ?? ?Print Version ?Bookmark and Share

Keywords:isopot? op-amp? LM13700? BJTs? diodes?

At vI = 4 V full-scale, U1A output current is 0.5 x IY = 50?A. U1B has the same full-scale x = 0.75, and its output current is 0.5 x (VP /R6) = 50?A. Then this current drops a voltage across R8 of (50?A)?(200 k次) = 10 V = VP .

Careful examination of the LM13700 specifications indicates from a graph labelled "Voltage vs Amplifier Bias [IY ] Current" that the current gain of the LM13700 amplifiers is significantly less than one in magnitude. After some calculation, the graph indicates that the gain is about ?2 to ?3 dB below unity gain, or about 20 to 30 % low. This results in the output of the circuit as correspondingly low and can be adjusted either by increasing the bias currents by this fraction (by reducing the value of R2) or by making RO = R8 that much larger.
Prototype verification
A prototype circuit was constructed as shown below. Test of this circuit is made easier by mounting ICs and BJTs in sockets. Then U1 can be pulled and a 10 k次, ㊣1 % resistor inserted into pins 6 (ground) and (in order of testing) 16, 15, 1, and 2. The voltage read at pins 16, 1, and 2 should be 1.00 V when VP+ ? VP? = 10 V. Adjust VR1 for 2.00 V at pin 15. Replace U1.

Apply a triangle-wave from a function generator to VI (connector pin 3) and ground (pin 4) and adjust for waveform extrema at 0 V and 4 V. BJT Q5 can be pulled and the 10 k次 test resistor placed from emitter to collector. Set the scope vertical input to ac coupling and measure about 0.5 V pk-pk at the emitter socket. Replace Q5 and observe control voltage and output voltage. They should appear as shown below, where trace 1 is the output and trace 2 is the input control voltage. The output pk-pk voltage should be 10 V but is about 6 V, a ?40 % error caused mainly by the low current gain of the LM3700 amplifiers.

If you are using a variable voltage supply for VP, varying it should vary the output amplitude accordingly. Also, an elevated VPcan be input by placing a floating 5 V supply in series with the VP supply. The output triangle-wave extremes should then be at 5 V and about 11 V, or 15 V after gain adjustment is applied to the design.

Closure
The rather high output resistance of this circuit can be reduced through an additional emitter-follower buffer stage. The simplest and least accurate way of doing this is to use one of the unused Darlington common-collector amplifiers in U1. The collectors of the Darlington stage connect to VCC.

The high-side range of VPWcan be readily extended with an additional supply that is 1 V to 5 V higher than VP+. Pot terminal loading is (R6 + R7)||R8 ? 100 k次. This can be reduced by changing the values of these resistors while observing the emulation constraints. As the voltage span, VP, varies, IYB also varies proportionally, maintaining emulation. At high common-mode voltage (VP+, VP- >> 0 V), the VPW node floats with it, up to the breakdown voltage of Q5 of about 60 V.


About the author
Dennis Feucht is an electronics engineer.


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