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Comparison of CPLD-based power mgmt architectures

Posted: 29 Feb 2016 ?? ?Print Version ?Bookmark and Share

Keywords:power management? processors? control PLD? DC-DC converter? VHDL?

There is now a strain to the capabilities of today's hardware/power management architectures due to the growing complexity of board-level designs. While any one of the four most commonly used management architecturesas described later in this papercan be used to support these complex designs, they each require different sets of compromises and design trade-offs in terms of scalability, design effort, and/or cost.

Recently, a fifth board management architecture has emerged that provides the best possible performance, safety, and flexibility while requiring far less design effort and implementation cost. This article will explore this new architecture, primarily with a focus on the power management functions it provides.

A circuit board is typically divided into two functional blocks (figure 1), the payload management section and the hardware management section. In most boards, 80 to 90% of the circuit board is typically devoted to "payload" functionality (data/control plane elements and/or processors). The remaining 10 to 20% of the board space is occupied by the circuitry that performs hardware-level monitoring/control or housekeeping functions.

Figure 1: In a typical electronic system, the hardware management elements occupy 10 to 20% of the board space (Source: Lattice Semiconductor)

Unfortunately, most existing hardware management solutions have difficulty scaling to address the growing complexity of modern payload elements. For example, although the hardware management section typically occupies only 10 to 20% of the board, its design/debug effort can consume a much larger percentage of the overall development time (30 to 40%). Likewise, the hardware manager often consumes a disproportionate share of the overall Bill of Materials (BOM) cost.

Recently however, a new distributed architecture has been developed that is much more scalable and can be implemented at a much lower BOM cost. In order to better understand the advantages a distributed architecture offers, we'll look at how power management is implemented in four of the most commonly used hardware management architectures before taking a deep dive into the new distributed architecture.

Power Architecture #1: Power management & housekeeping implemented using a control PLD
In this architecture, the power management functions are added to the on-board control PLD. The control PLD monitors the " Power-Good" signals of the input supply and each DC-DC converter (figure 2).

Figure 2: A hardware management system implemented using a control PLD to perform power management and housekeeping (Source: Lattice Semiconductor)

The sequencing algorithm implemented in a control PLD generates the sequence of "Enable" signals needed to turn on the power to the payloads without causing damage or logical errors. The control PLD also generates logical signals such as Resets and Power-Good signals to ensure that the payload devices can begin operation during power-up or terminate their operations during power-down. It is also responsible for generating a sequence to safely disable the supplies during power-down or when a fault is detected. PLDs can easily support event-based solutions, which provide different responses to different combinations of faults.

For this class of designs, all the power sequencing, protection and control functionality is implemented within the control PLD, typically using VHDL or Verilog.

???Low cost.
???Straightforward architecture enables the control PLD's sequencing logic to be easily scaled to accommodate new applications.
???Designs can be implemented using a single design environment (typically Verilog).
???Event-based architecture can respond to individual fault modes in a flexible manner.

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