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Enhancing receiver sensitivity

Posted: 02 Mar 2016 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? ADC? JESD204B? gallium arsenide? silicon germanium?

In modern communications systems, the more silent the input network the more sensitive the receiver can be. The receiver section of the system is very sensitive to noise being coupled in from other sources.

These noise sources can be the FPGA, the power supplies or the digital signals of the ADC itself. By designing a compact solution, barriers can be established between these noise sources and the analogue input to reduce the noise coupled into the input network and the sensitivity of the system can be improved.

A compact solution may not be possible with high power amplifiers that can dissipate 4 W of power. With improvements to the noise performance of the system, low noise amplifiers with high linearity feeding a quiet ADC are required to maintain the desired sensitivity. Several advances in ADC design such as the new JESD204B standard have helped designers tackle design challenges that previously have limited receiver sensitivity. These advances, coupled with the new low power amplifiers, ultimately improve system noise performance.

Amplifier design challenges
Traditionally, high frequency applications used gallium arsenide (GaAs) or indium phosphide (InP) gain blocks to achieve high linearity and low noise. These gain blocks require voltages between 9-12 V which leads to 2-4 W of power dissipation per receiver channel.

Cooling the receiver board becomes a challenge and can degrade the performance of the system if left unmanaged. In battery powered or low voltage applications, traditional gain blocks may be a problem due to the high power dissipation.

Some gain blocks, also require some input or output matching circuitry that may change depending on the frequency range of interest. This reduces the total bandwidth that a single network can receive and increases the design time required to match the input network.

Additionally, the majority of these gain blocks are single ended, which is inherently imbalanced. Imbalance in any system will result in even order harmonics that need to be filtered to achieve good linearity. In many situations the second order terms may be close to the edge of the passband where the attenuation of the filter is low.

Since the second order harmonic distortion is not attenuated in these situations, the sensitivity of the receiver is reduced. By using a differential gain block to begin with, a balanced network can be designed, and second harmonic distortion is less of an issue.

Amplifier solutions
In order to reduce the power consumption of the GaAs gain blocks while maintaining good linearity and noise performance, a different, lower power process is needed. The LTC6430 is a differential gain block, designed in a low power silicon germanium (SiGe) process that minimises the linearity and noise performance of high power gain blocks at a fraction of their power.

It operates from a 5V supply and draws only 160 mA of current, reducing the power consumption to less than 1 W. This reduction in power allows the LTC6430 to be used in low power, battery powered applications and in thermally sensitive applications in which a traditional gain block would not be appropriate due to the high thermal dissipation.

The LTC6430 is unconditionally stable with one matching network so all that is needed externally are DC blocking capacitors and RF bias chokes. This allows the LTC6430 to receive frequencies from 25MHz to 1600MHz with a single circuit.

This reduces the design time of the input network, allowing more time to be spent on other critical parts of the system. The simplicity of the LTC6430 matching circuit also reduces the required components as well as the complexity of the network between the ADC and amplifier, allowing for more room on the circuit board for barriers and vias to improve the results of the system.

The LTC6430 is a differential amplifier which naturally suppresses even order harmonics. The balanced nature of the LTC6430 produces cancellation of even order harmonics and improves the overall linearity of the system.

It also relaxes the attenuation requirement of the output filter between the amplifier and the ADC. The simplest possible balanced network between the ADC and amplifier will produce the best results by allowing room for barriers and vias to reduce interaction between the ADC and amplifier.

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