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Phase change memory advances: Threshold switching

Posted: 07 Mar 2016 ?? ?Print Version ?Bookmark and Share

Keywords:conduction? non-volatile memory? phase change memory? PCM? GeTe?

Pre-threshold switching delay time measurements is another piece of supporting evidence. It is well known that for PCMs the application of an over-voltage above Vt, the steady state switching threshold voltage, there is a delay time prior to switching. With the delay time inversely proportional to the over-voltage. The IBM team looked at this switching incubation time in detail. It was characterized by an increase in current just prior to switching indicative of pre-heating prior to the rapid transition. As shown in figure 1(c) a value of current reaching 40?A was used as the delay time marker.

For "dome" PCM structures the steady state simulation produced an interesting result it was the formation of hotspots or a hot torus at the edge of the bottom electrode as illustrated in figure 1(b). Although often ignored by others this would be expected from geometric considerations if as expected the "dome" structure was perfectly centred on the bottom electrode.

Dual switching effects possibility
As a point of discussion do these latest results now completely eliminate the possibility of the existence of a separate post-threshold switching conducting state that is not just hot amorphous material and which in a PCM device exists post-threshold switching and prior to the onset of crystallisation.

The appearance of such a state might be the cause of the transient in some threshold switching structures. For me there is one prime candidate and that is molten material. In figure 1(b) the rise time of the current is 24ns and does not appear to be particularly fast compared with some of the 1ns transients this writer and others have observed in the past with threshold switches.

To get the maximum crystal growth rate in the planar structure [Ref 4RGN IBM] some molten material will need be present during the SET operation. Other work from IBM [Ref 5 resistance spread] reported superior control of the SET state resistance distribution for PCM devices if melting is avoided when writing the SET memory state, indicating that some form of a post-threshold conduction state does exist for sufficient time for crystallisation to occur.

Is there a possibility that two mechanisms could be involved, where in some device structures the initial thermal threshold switching exposed by this latest IBM work and common to all devices acts in the role of a trigger. This provides access to a region of negative resistance which again in some devices is able to produces a transient current i = C dV/dt from any self or local stray capacitance which is able to deliver the power to create a molten hotspot . With the molten volume is maintained and expanded during the transient. The molten material would provide a conductivity discontinuity and its subsequent expansion provide a more powerful feedback mechanism and more rapid transient than would normally be obtained from thermal switching alone.

In the simple circuit as shown in figure 2 (a) with an integrated resistor of the type used in the IBM work the transient current is defined by the load resistor alone. However, when any self or stray capacitance is present 2(b) the transient current (dotted) is much larger and results in some localised melting. In that case the load resistor would act to latch the molten state of the hotspot and maintain some fraction of the volume of active material in the molten state as the current is reduced. Such dual switching effect might be the reason why sub 1ns transients were observed in the past for threshold switching and lead to the speculation and multitude of theories for purely electronic mechanisms.

Figure 2: With a close-coupled or integrated serial load resistor (Rser) the post-switching transient follows the load line, (b) any self or stray capacitance results in larger transient currents and more rapid switching.

I raised this as a possibility with the IBM team and IBM scientist Manuel Le Gallo offered the following insight,

"First note that the current rise time in a switching experiment is highly dependant on the voltage pulse parameters (width, leading and trailing edges) and amplitude. The slow rise time of 24ns is simply due to the fact that the voltage pulse was very short and had a low amplitude such that the

current rise time was well controlled to avoid any crystallisation or melting during the switching experiment. Much faster current rise times will occur for higher amplitude of the voltage pulse and if the device does not have a built-in series resistor or transistor to control the current. The same remark applies if a capacitor to ground is present between the device and the series resistor. The capacitor will slow down the transfer of the voltage drop from the device to the series resistor upon switching, which will effectively increase the switching speed."

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