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Achieve picosecond precision with FPGA techniques

Posted: 17 Mar 2016 ?? ?Print Version ?Bookmark and Share

Keywords:TDCs? FPGA? shifted clock sampling? buffer? PLLs?

Time to digital converters often find use in high energy physical experiments such as exploring subatomic level fine structure in fixed target experiments and collision experiments[1-2], where they need accuracy in the picosecond level. Designs are usually implemented with Application Specific Integrated Circuits (ASICs) for their high precision and stability compared with TDCs implemented on FPGA [3-4]. But TDCs based on FPGA also can reach picosecond precision [5]. TDCs implemented on FPGA need to take important features into consideration: quantisation step, measurement range, standard measurement uncertainty, non-linearities, dead time, and readout speed. There is an important guiding principle and trade-off in FPGA: the balance between size and speed [6]. We should consider high quality clocks and the placement of logic resources, resources consumption, and find ways to reduce non-linearity effects and calibrate the final results.

We first introduce the basic theory of TDC and then compare and analyse two popular TDC structures in Section II. In Section III we present a low resource consumption and high stability TDC with shifted clock sampling technique, multi-level latches, and four-level shift register arrays. The results are described in Section IV.

TDC architecture
Basic theory of TDC

Figure 1: TDC Timing Diagram.

?T = ?t1 + N*Tref?t2 (1)

The simplest design of TDC is the direct counting method, but in this way we only could measure the coarse time intervals between start and stop signals, while intervals ?t1 & ?t2 are ignored and bring about a 1 LSB measurement error. This scheme is also called "coarse counter", and the least significant bit (LSB) is determined by the frequency of the reference clock, namely LSB = 1/clk. The highest frequency in a FPGA is limited and generally only could reach approximately 500MHz.

Interpolator TDL and SCS
There are two schemes used to improve the resolution in the design of TDCs, namely tapped delay line (TDL) and shifted clock sampling (SCS). Both of them interpolate between clocks to determine ?t1 & ?t2.

Figure 2: Two kinds of TDC basic framework: (L) Tapped Delay Lines; (R) Shifted Clock Sampling.

For the TDL in figure 2, the delay chain is made up of a lot of delay units such as buffers or inverters. The shortest propagation delay of a logic gate in Virtex-5 may be only a few picoseconds, however, it is difficult to achieve a delay chain structure comprised of pure logic gate resources in an FPGA. Torres et al. [7] take advantage of the CARRY4 block as a delay element (in MUXCY of Xilinx FPGA), and better than 100ps accuracy is achieved.

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