Achieve picosecond precision with FPGA techniques
Keywords:TDCs? FPGA? shifted clock sampling? buffer? PLLs?
We first introduce the basic theory of TDC and then compare and analyse two popular TDC structures in Section II. In Section III we present a low resource consumption and high stability TDC with shifted clock sampling technique, multi-level latches, and four-level shift register arrays. The results are described in Section IV.
TDC architecture
Basic theory of TDC
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Figure 1: TDC Timing Diagram. |
?T = ?t1 + N*Tref?t2 (1)
The simplest design of TDC is the direct counting method, but in this way we only could measure the coarse time intervals between start and stop signals, while intervals ?t1 & ?t2 are ignored and bring about a 1 LSB measurement error. This scheme is also called "coarse counter", and the least significant bit (LSB) is determined by the frequency of the reference clock, namely LSB = 1/clk. The highest frequency in a FPGA is limited and generally only could reach approximately 500MHz.
Interpolator TDL and SCS
There are two schemes used to improve the resolution in the design of TDCs, namely tapped delay line (TDL) and shifted clock sampling (SCS). Both of them interpolate between clocks to determine ?t1 & ?t2.
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Figure 2: Two kinds of TDC basic framework: (L) Tapped Delay Lines; (R) Shifted Clock Sampling. |
For the TDL in figure 2, the delay chain is made up of a lot of delay units such as buffers or inverters. The shortest propagation delay of a logic gate in Virtex-5 may be only a few picoseconds, however, it is difficult to achieve a delay chain structure comprised of pure logic gate resources in an FPGA. Torres et al. [7] take advantage of the CARRY4 block as a delay element (in MUXCY of Xilinx FPGA), and better than 100ps accuracy is achieved.
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