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Investigating the impact of etching time on 4H-SiC defects

Posted: 31 Mar 2016 ?? ?Print Version ?Bookmark and Share

Keywords:Silicon carbide? SiC? etching time? stacking faults? photoluminescence?

Silicon carbide (SiC) shows potential as a semiconductor material for use in extreme conditions such as high power, high temperature and high frequency. Its attributes include wide band gap, high electric breakdown field, high thermal conductivity and high carrier saturation velocity. Although the degree of crystalline perfection of commercial 4H-SiC single crystal wafers has improved markedly in recent years, defects density is still high, and their replication from the wafer to the epitaxial layer grown on it is a serious impediment to device fabrication [references 1,2,3].

SiC's wide band-gap energy and low intrinsic carrier concentration allow to maintain semiconductor behaviour at much higher temperatures than silicon, which in turn permits SiC semiconductor device functionality at much higher temperatures than silicon [4]. In addition, SiC's high breakdown field and high thermal conductivity coupled with high operational junction temperatures permit extremely high-power densities and efficiencies to be realised in SiC devices. With remarkable improvement of SiC wafer quality and the progress in device technology, high-voltage SiC Schottky barrier diodes (SBDs) and field-effect transistors (FETs), which significantly outperform Si counterparts, have been enabled. These also include PiN rectifiers with blocking voltage close to 19 kV, Schottky diodes with breakdown higher than 1.5kV and MOSFET with breakdown voltage up to 1 kV.

The quality of substrate material is a crucial point for semiconductor technology in general and for SiC devices in particular. Using wafers with inhomogeneous surfaces containing mechanically disturbed and oxidized regions can result in a perturbed device performance (e.g. increase in recombination) or unpredictable degradation effects during operation. Commercial, mechanically-polished SiC wafers are known to be damaged and show a high density of scratches.

Previous studies show that proper surface preparation prior to the epitaxial growth will reduce the amount of surface defects on the substrates, which is the key for growing good quality epitaxial layers [5].Hydrogen etching is known to improve this situation by removing several hundred nanometers of bulk material [6,7].

S. Soubatch et al studied the effect of hydrogen (H2) vapor etching on the surface morphology and structure of on-axis 4H-SiC(0001) wafers in the temperature range from 1400C to 1600C. At high temperatures of 1600C two different etching mechanisms are active: namely, step-flow etching with full unit cell height steps on macro-terraces and etching of structural defects (e.g. screw dislocations). The best surface morphology, characterized by domains with a series of equidistant steps, develops at 1400C [8].

C. Hallin et al studied in situ preparation of 4H- and 6H-SiC substrate surfaces in hydrogen and hydrogen-propane etching systems [9]. The 4H on-axis surface is more irregular with large step formations and large etch pits, probably due to a high etch rate at defective zones. Micro-tubes running parallel to the surface and grain boundaries are enlarged, and triangular shaped etch pits have formed where micro-pipes and other dislocations penetrate the surface. Nevertheless, the hydrogen etching of 4H reveals many more extended stripe-like defects suggested to be stacking faults. Optimal etch conditions for the removal of scratches without leaving any traces of silicon droplets was obtained by adding propane to the hydrogen-flow.

In this experiment, the influence of the H2 etching time of the substrate surface on the defectiveness of 4H-SiC epitaxial layer has been studied. We also studied the influence of the etching time on the surface of the epi-layer through atomic force microscopy.

Experimental setup
For this experiment, homo-epitaxial growth was carried out in reactor using the SiH4/C3H8 system as Si and C supply, respectively. A high purity industrial grade H2 was used as a carrier gas as well as reducing agent for the growth of epitaxial layers. 10% N2 gas was added as a dopant. The reactor used in the experiment was a commercial low-pressure, hot-wall Chemical Vapor Deposition (LP-CVD) reactor by Tokyo Electron Limited (TEL). The n-SiC epitaxial layers with n-doping concentration of about 1E16 at/cm3 were grown on the Si-face (0001) 4H-SiC, n-type (~ 1018 at/cm-3) substrates with 4 off axis, towards [1 1 -2 0] in order to avoid formation of rough and mosaic patterns on the epitaxial layers [10]. For the experiment a 9.0 micron film epi-layer was grown, suitable for medium/high voltage diode or MOSFET technologies. Different H2 etching time has been investigated as half (x0.5), reference (ref), double (x2) and triple (x3) of the reference etching time. The doping concentration was 1E16 atm/cm3.

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