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EDA/IP??

Imagination focuses on secure, differentiated IP platforms

Posted: 31 Mar 2016 ?? ?Print Version ?Bookmark and Share

Keywords:Imagination Technologies? OmniShield? PowerVR? video encoder? HEVC?

Narayanan Rama, Business Development Manager for Connectivity at Imagination, said, "Communications, and connectivity are gradually being integrated on chip for many applications. Not only base band; in many cases even the RF functionality is integrated on the SoC." Therefore, with Ensigma RPUs, Imagination can provide end-to-end IP communication solutions from RF to base band, with the high performance Explorer family and the low-power Whisper family of RPUs.

"Ensigma Explorer emphasizes high performance and flexibility, and Ensigma Whisper has ultra-low power consumption," added Raman. "So far, the shipments of these two products have reached several million. Due to the integrated MIPS processor in the RPU, it is no longer necessary to use a dedicated host processor for all applications, thereby the overall system costs can be reduced, which is ideal for emerging wearable device applications."

Collaboration speeds design, verification optimised PPA

Synopsys has cooperated with Imagination for more than 10 years. According to Swee-Guan Ker, Synopsys Product and Solution Manager, 67% of the 'next designs' are at 32nm or less. Increasing design size, software complexity and software development as early as possible have become key challenges for SoC prototype designers. "In the process of cooperation, Synopsys' FPGA-based prototyping system HAPS, DesignWare HPC Design Kit, Verification Continuum and Galaxy Design Platform implementation tools including the layout and cabling solution IC Compiler II have played an important role," added Ker.

"When doing GPU prototype verification, the designers often face challenges in the following areas: quick and easy seamless migration between different GPU models; efficient verification and testing for independent GPU; and achieving good scalability when integrating the GPU into terminal application-oriented SoCs," said Ker. "By providing industry-leading, FPGA-based prototyping capacity and performance, and using intelligent partitioning and debugging tools, extended functionalities of Synopsys HAPS further reduce the time of software development and hardware/software integration."

The prototyping of PowerVR Series 6XT was done on the HAPS-70 system. HAPS-70 provides tightly integrated prototyping software and hardware, including HSTDM that can be used with new HapsTrak 3 I/O connector to provide a performance up to 3 times that of the traditional connector and pin multiplexing technology. By using a scalable architecture and Xilinx Virtex-7 FPGA devices, HAPS-70 supports a wide range of design sizes with capacity ranging from 12 million to 144 million dedicated ASIC gates.

The DesignWare HPC design kit includes a complete set of high-speed, high-density memory instances and standard libraries, which helps SoC designers optimise the on-chip CPU, GPU and DSP IP cores to achieve maximum speed, minimum area and lowest power consumption or achieve an optimal balance of the three depending on the specific application requirements.

According to Synopsys Senior FAE Henry Ren, for Imagination's 16FF+ PowerVR Series7 GPU, the kit achieved an area reduction of 5%, a power consumption reduction of 5%, and a performance increase of 5%, while shortening the cycle time by 30%.

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Figure 5: Synopsys and Imagination have collaborated for over 10 years, including using Synopsys' HAPS, DesignWare HPC Design Kit, Verification Continuum and Galaxy Design Platform with Imagination's IP cores.

Claimed to be the industry's fastest simulation system, the company's ZeBu Server-3 provides a high productivity environment for complex SoC verification. It also offers the industry's maximum design capacity (based on high-density 28nm FPGA architecture supporting up to 3 billion gates) and multiple verification modes, including power-aware simulation, simulation acceleration, online circuit simulation, synthesisable test bench, Transaction-Based Verification (VBT) and hybrid simulation that can be flexibly deployed according to project requirements.


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