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MOSFETs balance supercaps with zero power burn

Posted: 08 Apr 2016 ?? ?Print Version ?Bookmark and Share

Keywords:supercapacitor? MOSFETs? op amp? DC?

Many systems used in backup power storage or battery life extension are increasingly utilising supercapacitor series stacks. One of the most critical circuit design goals for such systems is minimising the steady state DC power dissipation. For that reason, MOSFETs deployed in circuits that balance voltage and leakage current in supercapacitor series-connected stacks of two or more can be configured to burn zero power.

To grasp the concept of zero power burn in balancing the individual supercapacitor cells, I will describe a circuit with current burn of 0.003 micro amperes (uA), or ~0.1% of 2.80 uA. While this is not absolute zero, the amount of energy used is so minimal that it is virtually zero. Using MOSFETs to balance voltage in supercapacitor cells stacked in a series contrasts to balancing voltage using op amp, which burns quiescent current.

Supercapacitors are becoming increasingly useful in high-voltage applications as energy storage devices. When an application requires more voltage than a single 2.7V cell can provide, supercapacitors are stacked in series of two or more. An essential part of ensuring long operational life for these stacks is to balance each cell to prevent leakage current from causing damage to other cells through over-voltage.

There are actually three possible scenarios of zero power burn of balancing circuitry. First, the power dissipated can be near zero, meaning that it is substantially less than a reference power dissipation level.

In this case, I use the highest leakage current within a group of a given make and model of supercapacitor as a benchmark reference power dissipation. The highest leakage current of one of the supercapacitors used is the actual minimum leakage current possible for the entire supercapacitor stack, not including any power used by any balancing component or circuitry.

Ten per cent of this reference current level can be selected as the threshold limit for zero power burn. An easy way to establish this reference current is to take the maximum leakage current specification from the supercapacitor manufacturer and use that as the reference current. A user can also establish his or her own reference current based upon the operating conditions that the system experiences, including, for example, temperature or ageing effects. All supercapacitors deployed in a system should first be independently tested for this reference leakage current.

The second scenario is that the possible power dissipation is actually zero at a steady state DC level.

The third scenario is that the power dissipation of the balancing circuit dissipates negative current burn of the supercapacitor stack, meaning that after the balancing circuits are installed, the total power burn is less than when there is no balancing circuitry. This is possible because MOSFETs operate by changing the balancing voltage bias of each of the supercapacitor in a series stack so that the highest leakage of the same benchmark supercapacitor is actually reduced by reducing its voltage bias after balancing is achieved. For any given supercapacitor, a reduced voltage bias reduces its leakage current level as well.

To understand how these three scenarios play out and achieve zero power burn, it is best to go through an example and analyse in three small steps what actually happens when a SAB MOSFET goes through its balancing act.

Supercapacitors connected in series with MOSFET auto-balancing
Figure 1 shows a pair of SAB MOSFETs placed across two supercapacitors. SAB MOSFET 1, or M1, is connected across C1, so input VIN1 of the SAB MOSFET is equal to supercapacitor voltage VC1. M2 is across C2 so VIN2 is equal to VC2.

Figure 1: Two supercapacitors stacked in series with MOSFETs.

There is leakage (bias controlled) current going through each one of the MOSFETs, referred to as lOUT1 for M1 and IOUT2 for M2.

Notice the equation, which states: V+ = VIN1 + VIN2 = VC1 + VC2. In other words, the two voltages across M1 and M2 are equal to the two voltages across both supercapacitors C1 and C2.

The total leakage current now becomes equal to IC1 + IOUT1 = IC2 + IOUT2.

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