Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

CAD tool for capacitance extraction in image sensor designs

Posted: 05 Apr 2016 ?? ?Print Version ?Bookmark and Share

Keywords:3D capacitance? Silicon Frontline Technology? ADC? analogue?

Silicon Frontline Technology has developed what it describes as a novel CAD tool for accurate 3D capacitance and distributed RC model extraction for image sensor designs. The F3D is a rigorous field solver based on stochastic random walk method, allowing capacitance extraction of complex 3D large-area structures such as pixels, arrays and precision analogue circuits (ADC, electrostatic shields, etc.).

Image sensor designs include many structures and circuits that are very sensitive to capacitive and resistive effects caused by metal interconnects and devices. These effects can be unintentional, i.e. parasiticsuch as floating diffusion (FD) node capacitance being impacted by parasitic capacitance between metal/contact/poly structures, or delays along clock or signal nets caused by distributed RC effects, or intentionalsuch as capacitance of MIM or MOM structures used in sample and hold circuits, ADCs and other circuits. F3D overcomes limitations of existing parasitic extraction tools and field solvers, and enables a predictive accurate capacitance extraction and distributed RC model generation, automated identification of all relevant capacitive coupling components, including long-range coupling, and detecting even small (down to 0.01 per cent or better) capacitance mismatch caused by layout effects.

Floating random walk method

Figure 1: Illustration of the floating random walk method as applied for capacitance extraction problem. A large number of random walks (consisting of a series of hops) are started from the Gaussian surface of a net to get a statistical estimate of the capacitance coupling between this net and all other nets.

Unique features of the F3Duser-definable capacitance calculation accuracy, meshless simulation method free from boundary condition and meshing artifacts, integration with standard physical verification flows, SPICE-compatible output (DSPF file), and ease of usemake it superior to existing popular parasitic extraction and field solver software tools. Application of F3D for calculation of floating diffusion (FD, or sense node) capacitance with varying metal layouts shows an excellent agreement with the measurement data. Examples of F3D application for other structures and circuits extraction are presented as well.

1???2?Next Page?Last Page

Article Comments - CAD tool for capacitance extraction ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top