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EDA/IP??

CAD tool for capacitance extraction in image sensor designs

Posted: 05 Apr 2016 ?? ?Print Version ?Bookmark and Share

Keywords:3D capacitance? Silicon Frontline Technology? ADC? analogue?

FD capacitance determines the pixel conversion gain, and it should be designed to a specific target value. Capacitance of small-size pixels is dominated by the coupling capacitances between the FD metal net and neighbouring metals. Capacitance tuning can be easily achieved through metal layout optimisation, provided that the capacitance extraction tool is reliable and accurate. F3D predicts the capacitance trend for varying metal layouts with absolute accuracy, and the total FD capacitance values with one-point calibration (F3D does not simulate semiconductor electrostatics and thus does not extract p-n junction and other non-linear capacitive semiconductor effects).

Walk method convergence

Figure 2: Illustration of random walk method convergence for calculated capacitance and reduction of statistical error of capacitance value with increase of the number of random walks

At the same time, F3D can be used as a general-purpose parasitic extraction tool providing guaranteed accuracy on large designs. One of breakthrough applications is super-high accuracy extraction of nets with nominally matched or weighted capacitances, such as in capacitor bank of SAR ADCs. Due to a close proximity of column ADCs (caused by pixel pitch constraint), parasitic coupling from the capacitor plates to the "outside world" violates prefect capacitance weighting and leads to integral and differential nonlinearities (INL and DNL) and loss of ADC resolution. F3D enables to detect capacitance mismatch as low as 0.01 per cent, to identify the root causes of the mismatch, and thus to achieve a more reliable and higher performance designs from first silicon. It should be noted that MIM and MOM capacitors can be treated as interconnects and simulated with F3D, to achieve higher accuracy, rather than relying on simplistic device models used with most parasitic extraction tools (based on area and periphery capacitance components).

Couplings between FD and neighbouring metals

Figure 3: Example layout showing couplings between FD and neighbouring metals


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