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Moore's Law extended: Intel roadmap reveals CMOS at its core

Posted: 07 Apr 2016 ?? ?Print Version ?Bookmark and Share

Keywords:Intel? CMOS? processor? SRAM? VCO?

The power to the SRAM arrays, when idle, is also being cured, so that 99 per cent of the array can be kept in sleep mode, while applying the low-or-high voltage supplies only to the SRAM cells being addressed at any one time, called dynamic sleep modes for SRAM.

Intel has also been continuously digitizing the analogue functions on its processors, because analogue circuits do not benefit from scaling like digital circuits. For instance the voltage scaling and temperature sensing circuits for power minimisation and to prevent thermal runaway, respectively, have been converted to digital circuits. For instance, analogue voltage controlled oscillators (VCOs) have been converted to digital voltage controlled oscillators (DCO), analogue transistors for bipolar junction transistors (BJTs) for thermal runaway sensing, along with all the other analogue functions inside the typical analogue phase-locked-loop (PLL) that looks in processor frequencies.

For circuits that Intel engineers have not yet figured a way to completely digitise, they are instead using hybrid mixed signal "digital assistance" techniques to optimise duty cycles, such as those used in its latest 14nm processors to boost input/output speeds to 40Gbit/s.

Future is adaptive design

The future of continued scaling is dependent on adaptive power management and voltage scaling, according to Zhang, which is needed to manage power with voltage scaling downward especially during sleep periods, but still with enough voltage to keep SRAM alive. Using a variable biasinstead of fixednext-generation transistors can be dynamically tuned using adaptive control biases that depending on the unique character of each chips' transistor so on each die produced.

Analogue circuits on processors

Figure 3: Intel is taking its formerly analogue circuits on its processors, here a temperature sensor, into completely digital circuits, such as using bipolar-junction-transistors (BJT) instead of analogue transistors and op-amps and converting the traditional voltage-controlled-oscillator (VOC) into a digital-controlled-oscillator (DOC). (Source: EE Times)

Today, if passive control is used to bias on-chip transistors, many die must be thrown away bus reducing yields, but with adaptive biasing control, those previously "bad die" can be optimised to perform just as well, or even better, by dynamically controlling their bias levels.

Adaptive voltage control will also be used to maximise performance and yields on nodes beyond 14nm by sensing exactly the right minimum supply voltage for SRAM sleep modes on a die for die basis. The optimal read and write voltages will also be adaptively be changed for lowest power and maximum performance during both read and write operations.

Core processors in traditional CMOS

Figure 4: Intel aims to keep its core processors in traditional CMOS, but surround it with new device architectures using new materials such as magnetic memories, Qubits, GaN transistors and whatever else proves to give leading edge advantages.

Beyond CMOS

For the future, Zhang believes that the CMOS cores, improved with the adaptive methods above, will remain the heart of future processors beyond 10nm. However, he also predicts that a potpourri of new materials, such as gallium nitride, magnetic materials, III-V materials, Qubits and more will serve as peripheral support technologies to its adaptive CMOS cores.

"Innovations continue to be the driving force into our future processors with CMOS remaining at is core," said Zhang. "Future technology scaling will demand even more innovative circuit designs to achieve optimal benefits in process, circuit and design automation, which need to be co-optimised for future success in technology scaling."

- R. Colin Johnson
??EE Times

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