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Machine learning methods is the future of chip routing

Posted: 11 Apr 2016 ?? ?Print Version ?Bookmark and Share

Keywords:ISPD 2106? FPGA? chip routing? machine learning? power distribution?

Auto-routing algorithms for a billion transistors chips will be a thing of the past, according to the International Symposium of Physical Design 2016 (ISPD, 2016, April 3-6, Santa Rosa, Calif.), as chip routing will be covered by the fastest machine learning methods. ISPD 2016 closed its sessions with an awarding ceremony for best solution to its annual design contest and its best paper awards, featuring machine learning of a power distribution network.

The ISPD 2016 contest was for the first time a routing problem for interconnecting a field-programmable gate array (FPGA). With Xilinx as the sponsor, the contest involved using a Xilinx' XCVU095 FPGA, a part in the 20-nanometer Virtex UltraScale family (the XCVU095 has 67,200 configurable logic blocks (CLBs), 880 input/output (I/O) locations, 770 multiplier (DSP) locations, and 1730 block random access memory (BRAM) locations.

Xilinx FPGA

Figure 1: The VU095 ultra-scale Xilinx field programmable gate array (FGA) used in the contest. (Image source: EE Times)

"The benchmarks for ISPD 2016 placement contest were generated using an internal netlist-generation tool based on Generate NetList (Gnl). The tool allows us to create netlists of different placement and routing complexities by varying the number of components and their interconnection. Additionally, it provides control over the type of components (primitives) used in the netlist. For ISPD benchmarks, we have restricted the primitives to be look-up-tables (LUTs), flip-flops (FFs), DSP blocks (DSPs), and block RAMs (BRAMs)," according to the paper "Routability-Driven FPGA Placement Contest", by Stephen Yang, Aman Gayasen, Chandra Mulpuri, Sainath Reddy, Rajat Aggarwal (Xilinx)

ISPD 2016 winners

Figure 2: 1st Place winners of ISPD 2016 FPGA routing problem are David Pan, Wuxi Li and Shounak Dhar awarded by conference chair, Evangeline Young, left to right. (Image source: EE Times)

"The Routability-Driven FPGA Placement problem had 19 initial entrants, with 12 submitting solutions, which we narrowed down to five, all of which were invited to ISPD 2016," said Yang.

ISPD Yang

Figure 3: Co-author of the paper "Routability-Driven FPGA Placement Contest" describing the contest and how it was judged. (Image source: EE Times)

The final winner was the University of Texas (Austin) with its UTPlacer built by Wuxi Li, Shounak Dhar and David Pan. All contestants used the Xilinx Implementation Tool flow (Vivado), which converted their design into a configuration bitstream which was loaded onto the FPGAs SRAM to realize their design.

Best Paper Award

This year's best paper award went to a doctoral candidate of legendary IEEE Fellow Yao-Wen Chang. His student, Wen-Hsiang Chang (no relation) at National Taiwan University (NTU). Yang won the best paper award with a little help from his friends (Li-De Chen from National Taiwan University, Chien-Hsueh Lin, Szu-Pang Mu and Mango C.-T. Chao from National Chiao-Tung University, Hsinchu, Taiwan, along with Cheng Cheng-Hong Tsai and Yen-Chih Chiu from Global Unichip Corporation, also Hsinchu, Taiwan.

NTU Wen-Hsiang Chang

Figure 4: Wen-Hsiang Chang a doctoral candidate at the National Taiwan University (NTU) won the best paper award for his machine learning approach to routing in "Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique" (Image source: EE Times)

The paper, titled "Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique" was a breakthrough, according to the judges.

"Our power distribution network not only used machine learning for optimisation, but also used some predictors to quickly narrow down the possibilities, giving our technique and advantage," said Chang.

Many tools have been invented to automate the routing of power distribution networks, but Chang and associates used machine learning to pick the optimal configuration from among a set of candidates that were prescreened. Its novel prescreening technique sped up the machine learning search process by first calculating the total length of wire needed for a particular power distribution network (PDN) "an easy task" which turned out to be an accurate predictor that could quickly narrow down the field to the PCNs that needed to be compared regarding which was the most optimal.

- R. Colin Johnson
??EE Times





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