Data inspection techniques for massive memory designs

The demand for large data storage and high speed access has grown dramatically in the semiconductor industry with the simultaneous need to reduce data footprint for effectively managing more infrastructure resources. In two decades alone, we have witnessed the evolution of electronic devices from desktop computers to laptops to servers, tablets, smartphones, and high performance processors/graphics-accelerators/network devices. Accordingly, memory requirements have evolved from 32MB PC-66 SDRAM memory clocking @66Mhz (does anyone even remember those days?) to 1 TB DDR4-3000 memory clocking @3000Mhz and beyond.

To meet the goals of less power consumption in smartphones and tablets, a new system called LPDDR (Low Power DDR) is gaining currency. For high end smartphones, wide I/O is designed which contains up to 1024 bits wide bus for high performance and uses vertical stack and interconnects to minimise electrical interference and die footprint. To meet next generation high-performance and gaming/graphics accelerators, and network devices, HMC (Hybrid Memory Cube) and HBM (High Bandwidth Memory) have been designed which have multiple lanes/channels/ports to support 256Gbit/s bandwidth and multiple dies to store 8Gb and beyond.

In older SDRAM DDR designs, we still traditionally use parallel, single-ended interfaces whereas for next-generation high performance requirements, multi-channel interfaces are designed in HBM DDR. This trend has caused an upsurge in the complexity of storage designs and a proper verification stratagem is needed to meet time-to-market for product launches in short time span, and with functional correctness. This article discusses efficient data inspection techniques that will help you reduce the verification stint in a large storage high bandwidth DDR-based memory design using latest System Verilog-based UVM verification methodology.

Design overview
A conventional design includes various IP blocks which use Memory Controller (MC) Ports [MC1 to MC8] to access DDR memory. MC Ports are connected to an Arbiter which is connected to two Memory Controllers via high-speed bus interface which help access DDR Memory as shown in figure 1. Hefty bursts of Write & Read Data transactions are generated from various MC ports and Arbiter will process them as per port priority which will then be routed to lower or upper memory controller and then onto DDR memory on high speed bus interface.

Verification requirements
We have eight MC Ports which independently access 128GB of memory storage space while splitting into lower & upper DDR Memories. One Write or Read Transaction is worth 64bits (8B) in size. Ideally, we will first have a Write Transaction followed by a Read Transaction on any memory location. But in this context, there can be three types of scenarios that have to be considered while accessing any memory location.

1. Read followed by Write Transaction
2. Two or more Write Transactions without any Read
3. Read Transaction before Write Transaction

So, in order to verify all transactions, the traditional method of self-checking back data Read after Write will not help since the same location can be accessed by various MC Ports depending on the timings and Arbiter priority scheme. To validate whether the Write Transaction from MC Port has reached the same location in DDR Memory, it must be captured at both the MC Port & DDR interfaces. If Read is issued afterwards on the same memory location, the data expected to be captured on Write should be compared with actual Read data. So, there will be two scoreboards—one on MC Port and the other one on DDR interface as shown in figure 2, which would in turn, compare Read data against expected Write data.