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Guard against latchup in CMOS chips

Posted: 25 Apr 2016 ?? ?Print Version ?Bookmark and Share

Keywords:CMOS? power supply? analogue-to-digital converter? ADC? Latchup?

Don't laugh, it has happened to a lot of good engineers, and you might be next. Since CMOS circuitry needs so little power, the inputs can flip the internal ESD diodes around and you will not only power the chip's Vcc line, that Vcc line connects to all the other chips and they will be powered up too. So then you risk latching up the first IC and you are not really saving power in the first place.

The physics of latchup
Years ago, when I was at National Semiconductor, I came across a nice simplified die diagram that purported to explain latchup (figure 3). I loved it since the colour-coding would relate the die areas with the emitters, bases, and collectors of the parasitic transistors that form when the part goes into latchup. I dragged the diagram out and was going to use it again for this article. Fortunately I went to the third floor to ask IC designer Scott Fritz if the diagram made sense. Scott is a fellow analogue aficionado, and was quick to point out many deficiencies and over-simplifications in the diagram. I knew it was off-base when he said, "The substrate is usually P-type silicon with an N-type well."

Figure 3: A CMOS gate has a P-channel FET on top and an N-channel one on the bottom. The die diagram shows how process engineers make these transistors. But there are also parasitic bipolar transistors formed by the structures, shown on the far right. The colours of the semiconductor structures match the colour of the schematic elements. With the connections on those parasitic bipolar transistors, you can see once a little current starts to flow, it will feed off itself until the device melts.

With Scott's direction, I worked up a much better diagram (figure 4). I made the substrate of the transistor pair out of P-type material, and put the upper transistor in an N-well. Scott noted that while op-amps will use plus and minus power, it is easier to just think of power and ground for most CMOS circuits. The other major mistake of the first diagram was that it did not show the power and ground connections to the N-well and the P-substrate. Scott explained that for output transistors you might have only one P-channel transistor in the N-well, but typically there are dozens or hundreds. The reason I had misgivings about that first diagram was that it showed the parasitic transistors, but it really did not show the mechanism of how the latchup occurs, how you get those parasitic NPN and PNP transistors to form in your CMOS chips.

Figure 4: An improved diagram shows the wafer substrate as the more typical P-type material. You run most CMOS circuits single-ended, with just power and ground. Also shown are the P+ and N+ connections needed to apply bias between the N-well and the substrate.

After Scott explained that the N-well is hooked to Vcc and the substrate is hooked to ground, he pointed out those connections add two resistors to the equivalent circuit on the right side of the figure. He then came at the problem from an IC designer's perspective. He said there are two primary things an IC designer wants to do to prevent latchup. One is to make those resistors as low-valued as possible. The other is to make the beta (?, or current gain) of the parasitic transistors as low as possible.

Note that the bias, the power applied between the N-well and the substrate, means any free electrons in the substrate will seek that ground. Similarly any free holes in the substrate will seek Vcc. If the only path is through those parasitic emitters, then boom, the part will latch. So having those resistors that are formed by the N+ to N and the P+ to P paths be as low value as possible will provide a shunt path around the emitters to let the free carriers seek power and ground.

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