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Guard against latchup in CMOS chips

Posted: 25 Apr 2016 ?? ?Print Version ?Bookmark and Share

Keywords:CMOS? power supply? analogue-to-digital converter? ADC? Latchup?

Since the resistor's value is directly proportional to the distance the free carriers have to travel. Fritz noted that my improved diagram is drawn for clarity, but the best way to reduce the values of the resistors was to add a second N+ pad to the other side of the N-well and move the P+ pad to the other side of its transistor (figure 5). The two resistors in the N-well parallel and reduce the effective resistance. Moving the P+ pad in the substrate puts it very close to the substrate material that acts as the base of the NPN parasitic transistor. I asked why you need N+ and P+ to begin with. Scott explained that if you just hook metallisation to the N-type material it forms a Schottky diode. The greater impurities in the N+ and P+ material makes the silicon more metallic and the connection to the metallisation becomes galvanic.

Figure 5: An IC designer can ameliorate latchup problems by lowering the equivalent resistors in the right-side diagram. She does this by putting two N+ pads in the N-well, so the two resistors parallel in value. For the lower transistor, she can move the P+ pad where it is closest to the effective base area in the substrate. In addition to lowering the resistances, it is important to make the current gain of the parasitic NPN and PNP transistors as low as possible.

The other way to prevent latchup in CMOS circuits is to reduce the beta of the parasitic transistors. If you remember your transistor physics class, after a few whiteboards' worth of equations, the beta of a bipolar transistor is directly proportional to the thickness of the base area the free carriers are being swept through by the applied voltages. Looking at figure 4 again, the easiest way to make the base of the lower NPN parasitic transistor thick is to move the whole CMOS N-channel device away from the upper P-channel device. Now there is a lot of orange-coloured substrate between the two devices, and that means the parasitic base is very thick and the beta is very low.

There is no simple IC design trick to reduce the beta of the top parasitic PNP transistor. This is a vertical PNP since the P, the N, and the P areas are arranged vertically in the die (note the figure has the die cross-section standing on edge to mimic the arrangement of the schematic). The beta of the parasitic PNP transistor is fixed by the thickness of the N-well between the P+ source connection and the substrate. That is a function of the semiconductor process, but Fritz assures me it is well-controlled and predictable, despite being set by diffusion and not lithography.

There is an economic benefit to having thin wafers since you can cut more of them from a silicon crystal ingot. But the practical mechanical limit on wafer thickness still allows process engineers plenty of room to make the N-well deep enough to ensure the beta of the parasitic PNP transistors is very low. Another batch of mathematics will show that you have to keep the product of the two transistors' betas below 1 to prevent latchup. Since it is easy to make the NPN beta very low, the beta of the PNP can be above 1 but when multiplied by, say, the 0.25 beta of the NPN transistor, the product is still less than one.

Beta increases with temperature, and an IC designer has to factor that into his design. Beta is also higher with low collector currents. A CMOS device on the edge of latchup has miniscule collector current to begin with, so the beta is high. Once the part latches, the currents go way up, but it is too late; once the latchup begins the part will melt unless something external limits the current, perhaps the bond wires melting. Neither situation is a desirable design result.

The mechanisms of latchup
Now that you understand the physics of latchup, you can see how it starts. This is what was unsatisfactory in the first diagram, it showed the parasitic transistors you end up with, but not how they get formed out of a CMOS circuit made from MOSFETs. Looking at figure 4 (shown again below), imagine that you take the output pad and drag it below ground. That blue N+ pad will now sink current once you get past the P-N diode drop voltage, about 0.6V. The orange substrate material will be full of electrons and they will seek ground through the green N+ parasitic NPN emitter pad. An analogous situation happens in the N-well when you pull the output above Vcc. The free carriers in the base regions of the parasitic bipolar transistors are all you need to start the latchup, and once it begins it just feeds on itself.

This is one reason switching a chunk of CMOS circuitry on and off to save power can cause latchup. If you turn off Vcc, a volt applied to the output will cause current to flow, perhaps as it drags the Vcc voltage up, but current flows nevertheless. When your power management system re-applies power, boom, the part is in latchup.

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