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The ideal union of PAM and Ethernet

Posted: 16 May 2016 ?? ?Print Version ?Bookmark and Share

Keywords:Ethernet? pulse amplitude modulation? PAM? physical layer? media access control?

PAM5 signalling is used across various Ethernet speeds, such as 100BASE-T2 and 1000BASE-T. It uses these two pairs for simultaneously transmitting and receiving on both pairs thus allowing full-duplex operation. First, a 4bit symbol is expanded into two 3bit symbols through a non-trivial scrambling procedure based on a linear feedback shift register. The mapping of the original bits to the symbol codes is not constant in time and has a fairly large period (appearing as a pseudo-random sequence). The final mapping from symbols to PAM5 line modulation levels conform to the figure 5.

Figure 5: PAM5 Constellation.

PAM8 signalling targets 100G PHY. For the PAM8 scheme, the bit stream is mapped into symbols via a PAM8 encoder then a simple 3 tap T spaced FFE filter is used to perform pre-distortion, with T being the symbol period.

This signalling is used in various Ethernet speeds; such as 2.5G BASE-T, 5G BASE-T, 10G BASE-T, 25G BASE-T, 50G BASE-T. The IEEE standard specifies the wire-level modulation for 10G/25G/50GBASE-T to use THP and PAM with 16 discrete levels (PAM16), encoded in a two-dimensional checkerboard pattern, known as DSQ128, sent on the line at 800 Msymbols/s.

Figure 6: DSQ-128 Constellation Used in PAM16.

The standard specifies the wire-level modulation for 2.5G/5G BASE-T to use Grey Coding mechanism for 16 discrete levels.

Table 2: Questa Verification IP.

Mentor Graphics provides an Ethernet Questa Verification IP (QVIP) solution for the whole ecosystem. Ethernet QVIP is a UVM-based multi-level abstraction VIP that provides verification and debugging of memory systems. Ethernet QVIP also include OVM, UVM, SystemVerilog, Verilog, VHDL, and SystemC based testbenches that allow users to integrate QVIPs with their designs. All QVIPs provide comprehensive coverage plans and include assertions to ensure all specification violations are logged.

Ethernet QVIP supports various PAM encoding speeds like 10MBASE-T, 10GBASE-T, and 2.5GBASE-T. It can be configured to have a scrambled data path or unscrambled data path. QVIP can be dynamically configured to any speed during a reset condition and achieve the desired interface speed through successful negotiation following the process of auto-negotiation.

Figure 7: PAM in QVIP.

Error scenarios are fundamental to the design verification effort. Error scenarios help users verify design behaviour and its recovery procedure. Such errors can involve invalid CRC, invalid code groups and symbols, and more. QVIP provides error injection mechanisms appropriate to all types of error for memory design

All projects that have modulation algorithms can utilise PAM as their transmission scheme due to its high data rate, its simplicity, and ease of transmission. The adoption of PAM across various Ethernet speeds is a result of emerging market requirements for ease of circuitry.

Ethernet QVIP provides verification and debugging that Ethernet designers require. Ethernet QVIP supports various Base-T speeds and advanced verification featuressuch as coverage collection, assertion checking, and scoreboarding. QVIP is touted to reduce the time it takes for engineers to set up verification runs, so they can focus on verifying the unique, high-value parts of their designs.

About the author
Nikhil Jain is an engineer at Mentor Graphics India.

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