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Benefits of adding isolation to LVDS interfaces

Posted: 18 May 2016 ?? ?Print Version ?Bookmark and Share

Keywords:Galvanic isolation? interfaces? analogue front-ends? Internet of Things? IoT?

By contrast, as shown in figure 2, Analog Devices has introduced a family of drop-in LVDS isolators, ADN4650/ADN4651/ADN4652, using iCoupler technology enhanced for operation up to 600Mbit/s. In addition to TIA/EIA-644-A LVDS compliant I/O, the complete isolator signal chain is fully differential, realising a high-immunity and low emissions solution. Two isolated LVDS channels are provided, one transmit and one receive (ADN4651, or vice-versa for ADN4652) or two transmit or receive (ADN4650). The internal high-speed circuits operate at 2.5 V, which may not be present in industrial systems as a power rail, so internal low drop-out regulators (LDOs) are provided (as shown in figure 3) to allow a single wide-body SOIC solution even when powering from 3.3 V supplies.

Figure 2: ADN4651 600Mbit/s LVDS isolator block diagram.

Are these new LVDS isolators a drop-in solution?
In order to guarantee these LVDS isolators can be inserted into converter-to-processor interfaces, or intra-processor links that operate up to 600Mbit/s, the ADN465x family has precision timing with ultra-low jitter. This is important because at 600Mbit/s, the unit interval (UI, i.e. the bit time) is only 1.6 ns, so any jitter on the edges must still allow enough time for the receiving component to sample the bit. Typical total jitter is 70 ps for the ADN465x, or -12.

How to quantify jitter
The most basic method of viewing jitter is to measure an LVDS signal pair with a differential probe and trigger on both rising and falling edges, with the oscilloscope set to infinite persistence. This means that high-to-low and low-to-high transitions are superimposed, allowing measurement of the "crossover" point. The width of the crossover corresponds to the peak-to-peak jitter or time interval error (TIE) measured so far (compare the eye diagram and histogram shown in figure 3. Some jitter is due to random sources (e.g. thermal noise) and this random jitter (RJ) means that the peak-to-peak jitter seen on the oscilloscope is limited by the run time (the tails on the histogram will grow as the run time increases).

Figure 3: Eye diagram and histogram for ADN4651.

By contrast, sources of deterministic jitter (DJ) are bounded, such as jitter due to pulse skew, data-rate dependant jitter (DDJ) and intersymbol interference (ISI). Pulse skew arises due to a difference between high-to-low and low-to-high propagation delays. This is visualised by an offset crossover such that at 0V, the two edges are separated (easily seen by the separation in the histogram in Figure 3). DDJ arises from a difference in propagation delay across operating frequency, while ISI arises due to the influence of previous transition frequencies on the current transition (i.e. edge timing will typically be different after a train of 1s or 0s vs. a 1010 pattern).

In order to fully estimate the total jitter for a given bit error rate (TJ@BER), RJ and DJ can be calculated based on model-fitting to a TIE distribution from measurement. One such model is the dual-Dirac model, which makes an assumption of a Gaussian random distribution convolved with a dual Dirac-delta function (the separation between the two Dirac-delta functions corresponding to the deterministic jitter). For TIE distributions with significant deterministic jitter, the distribution will visually approximate this model. One complication is that some deterministic jitter can contribute to the Gaussian component, meaning that dual-Dirac can underestimate deterministic jitter and overestimate random jitter. However, the two combined will still allow an accurate estimate of the total jitter for a given bit error rate.

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