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TMS320C6455 Fixed-Point Digital Signal Processor (Rev. H)
Texas Instruments

The TMS320C64x+? DSPs (including the TMS320C6455 device) are the highest-performance fixed-point DSP generation in the TMS320C6000? DSP platform. The C6455 device is based on the third-generation high-performance, advanced VelociTI? very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+? devices are upward code-compatible from previous devices that are part of the C6000? DSP platform. Based on 90-nm process technology and with performance of up to 9600 million instructions per second (MIPS) [or 9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the C6455 device offers cost-effective solutions to high-performance DSP programming challenges. The C6455 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At a 1.2-GHz clock rate, this means 9600 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle. The C6455 device includes Serial RapidIO. This high bandwidth peripheral dramatically improves system performance and reduces system cost for applications that include multiple DSPs on a board, such as video and telecom infrastructures and medical/imaging. The C6455 DSP integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on the C6455 device are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. The level 2 (L2) memory is shared between program and data space and is 2096KB in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. The C64x+ Megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp. The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as ......
High-Performance Fixed-Point DSP (C6455) 1.39-, 1.17, 1-, and 0.83-ns Instruction Cycle Time 720-MHz, 850-MHz, 1-GHz, and 1.2-GHz Clock Rate Eight 32-Bit Instructions/Cycle 9600 MIPS/MMACS (16-Bits) Commercial Temperature [0C to 90C] Extended Temperature [-40C to 105C] TMS320C64x+? DSP Core Dedicated SPLOOP Instruction Compact Instructions (16-Bit) Instruction Set Enhancements Exception Handling TMS320C64x+ Megamodule L1/L2 Memory Architecture: 256K-Bit (32K-Byte) L1P Program Cache [Direct Mapped] 256K-Bit (32K-Byte) L1D Data Cache [2-Way Set-Associative] 16M-Bit (2096K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation] 256K-Bit (32K-Byte) L2 ROM Time Stamp Counter Enhanced VCP2 Supports Over 694 7.95-Kbps AMR Programmable Code Parameters Enhanced Turbo Decoder Coprocessor (TCP2) Supports up to Eight 2-Mbps 3GPP (6 Iterations) Programmable Turbo Code and Decoding Parameters Endianess: Little Endian, Big Endian 64-Bit External Memory Interface (EMIFA) Glueless Interface to Asyncs Memories (SRAM, Flash, and EPROM) and Synchronous Memories (SBSRAM and ZBT SRAM) Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.) 32M-Byte Total Addressable External Memory Space Four 1x Serial RapidIO? Links (or One 4x), v1.2 Compliant 1.25-, 2.5-, 3.125-Gbps Link Rates Message Passing, DirectIO Support, Error Management Extensions, and Congestion Control IEEE 1149.6 Compliant I/Os DDR2 Memory Controller Interfaces to DDR2-533 SDRAM 32-Bit/16-Bit, 533-MHz (data rate) Bus 512M-Byte Total Addressable External Memory Space EDMA3 Controller (64 Independent Channels) 32-/16-Bit Host-Port Interface (HPI) 32-Bit 33/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Local Bus Specification (version 2.3) One Inter-Integrated Circuit (I2C) Bus Two McBSPs 10/100/1000 Mb/s Ethernet MAC (EMAC) IEEE 802.3 Compliant Supports Multiple Media Independent Interfaces (MII, GMII, RMII, and RGMII) 8 Independent Transmit (TX) and 8 Independent Received (RX) Channels Two 64-Bit General-Purpose Timers, Configurable as Four 32-Bit Timers UTOPIA UTOPIA Level 2 Slave ATM Controller 8-Bit Transmit and Receive Operations up to 50 MHz per Direction User-Defined Cell Format up to 64 Bytes 16 General-Purpose I/O (GPIO) Pins System PLL and PLL Controller Secondary PLL and PLL Controller, Dedicated to EMAC and DDR2 Memory Controller Advanced Event Triggering (AET) Compatible Trace-Enabled Device IEEE-1149.1 (JTAG?) Boundary-Scan-Compatible 697-Pin Ball Grid Array (BGA) Package (ZTZ or GTZ Suffix), 0.8-mm Ball Pitch 0.09-?m/7-Level Cu Metal Process (CMOS) 3.3-/1.8-/1.5-/1.25-/1.2-V I/Os, 1.25-/1.2-V Internal All trademarks are the property of their respective owners.

Related Datasheets
Part Number Description Category
? ?TMS320C6416T TMS320C6414T, TMS320C6415T, TMS320C6416T Fixed-Point Digital Signal Processors (Rev. L) EDA - IC Design
? ?TMS320C6424 TMS320C6424 Fixed-Point Digital Signal Processor (Rev. B) EDA - IC Design
? ?TMS320C6452 TMS320C6452 Digital Signal Processor EDA - IC Design
? ?TMS320C6454 TMS320C6454 Fixed-Point Digital Signal Processor (Rev. D) EDA - IC Design
? ?TMS320DM355 TMS320DM355 Digital Media System-on-Chip (DMSoC) (Rev. D) EDA - IC Design
? ?TMS320DM642 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor (Rev. L) EDA - IC Design
? ?TMS320DM6437 TMS320DM6437 Digital Media Processor (Rev. C) EDA - IC Design
? ?TMS320DM6446 TMS320DM6446 Digital Media System-on-Chip (Rev. E) EDA - IC Design
? ?TMS320DM6467 TMS320DM6467 Digital Media System-on-Chip EDA - IC Design
? ?TMS320DM648 TMS320DM647/TMS320DM648 Digital Media Processors (Rev. A) EDA - IC Design

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