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| 2011-01-21 | PDK and reference flow for 0.18um power management process Tanner EDA and TowerJazz announce PDK for 0.18um power management process. Kit includes symbol libraries for schematic capture software as well as parameterized layout generators for L-Edit. |
| 2013-11-27 | MagnaChip, YMC tout 0.35um, 0.18um embedded MTP IP sol'ns The solution covers several standard memory cell sizes and is intended for embedded applications such as display, PMIC and LED controllers. |
| 2015-01-14 | MagnaChip offers 0.18um automotive process technology The 0.18um process technology aims at automotive semiconductor applications. It enables operation at high temperatures and complies with AEC-Q100 specification. |
| 2013-05-10 | Magnachip adds 30V option to its 0.18um EEPROM The additional high voltage option provides increased noise immunity by improving the signal-to-noise ratio characteristics of devices, a critical issue in touch sensing IC performance. |
| 2014-11-10 | 0.18um low power manufacturing process aimed at IoT The low-power premium process from MagnaChip targets mobile, wearables, wireless sensors and energy harvesting applications, which are crucial for the growth of Internet of Things space. |
| 2007-04-24 | Report: Taiwan should reassess chip regulation with China The U.S.-Taiwan Business Council's semiconductor quarterly report for Q1 calls for Taiwan's reassessment of its chip regulation with China. |
| 2007-01-15 | Novocell nonvolatile memory IP in 0.18?m CMOS Novocell Semiconductor announced its NovoBlox OTP memory IP, implemented in a patented, gate oxide antifuse technology. |
| 2002-07-18 | 1st Silicon to adopt Virtual Silicon's semiconductor IP Virtual Silicon Technology Inc. has received an order to port its semiconductor IP to the 0.185m process technology of Malaysia wafer foundry 1st Silicon. |
| 2004-05-19 | Toshiba to apply Sarnoff's TakeCharge IC design Toshiba Corp. has revealed that it will implement the TakeCharge on-chip electrostatic discharge (ESD) design approach from Sarnoff Corp. in its CMOS IC processes (0.18?m, 0.13?m, 90nm and 65nm process technology). |
| 2013-01-17 | Thick plated copper process for monolithic PMIC apps UMC's TPC solution provides thick plated copper layers to achieve higher current flow and better thermal dissipation to cut chip resistance, extending battery life. |
| 2006-05-31 | Rising unveils RF transceiver chipset for 3G WCDMA handsets Rising Micro Electronics announced that it has successfully developed RF transceiver chipset for 3G WCDMA wireless handsets using Jazz Semiconductor's 0.18m SiGe BiCMOS. |
| 2012-01-05 | Mobile tech: Good for batteries, good for Asia The mobile consumer market will add $309 billion to the semiconductor market by 2015, and much of this growth will be spurred by innovations within the power management sector. |
| 2015-02-03 | MagnaChip adds high voltage option to 0.13-micron embedded EEPROM The 0.13?m embedded EEPROM IP boosts the performance of touch controller ICs and MCUs by decreasing the density of 32KB memory blocks by about 50 per cent and by adding a high voltage option. |
| 2014-04-16 | GigOptix ASIC expansion addresses designs in lower nodes GigOptix has released an ASIC product series that provide benefits including low production costs and rapid design cycles. |
| 2014-02-03 | Europractice MPW service features high voltage process X-Fab, an analog and mixed-signal foundry, teamed with Imec to allow its Europractice IC service to offer a couple of high-voltage processes for manufacture using multi-project wafer runs. |
| 2014-01-03 | eMemory, SMIC extend eNVM dev't deal The firms plan to expand the deployment of their collaboration on SMIC's embedded non-volatile memory platform development that covers both OTP and MTP eNVM technologies. |
| 2013-11-15 | Ams offers cost-efficient IC prototyping service The prototyping service, known as Multi-Project Wafer (MPW) or shuttle run, claims to deliver significant cost advantages for foundry customers. |
| 2014-06-09 | ADI holds on to manufacturing amid IoT rise Analog Devices manufactures some chips in house where it feels the design is closely tied to the manufacturing process and where it feels it is only adding value in standard design, it outsources. |
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