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2013-07-09 USHIO books its interposer stepper for 2.5D/3D packaging
The UX7-3Di LIS 350 has achieved a resolution of 2?m L/S on a 300mm Si wafer as well as an organic substrate and is able to address a warp or expansion/contraction of an organic substrate.
2013-04-02 Nvidia will push for 2.5D stacks on organic substrates
Organic substrates with new I/O techniques could pave the road to a 2.5D chip stack for Nvidia, said R&D VP William Dally.
2012-03-07 Introduction to 2.5D
We need evolutionary, instead of revolutionary, adjustments to current design flows and the supply chain to successfully leverage 2.5D.
2015-03-06 Intel recommends 2.5D, 3D integration for next-gen chips
Intel emphasised that heterogeneous integration enabled by 3D IC is essential to the development of future SoCs, especially in terms of scaling lithography processes.
2013-04-02 IME, UTAC team up for 2.5D TSI packaging solutions
United Test and Assembly Center will collaborate with A*STAR's IME to develop a 2.5D Through-Silicon-Interposer (TSI) platform for packaging solutions.
2011-12-07 IME, Tezzaron develop "2.5D" interposer tech
A*STAR Institute of Microelectronics and Tezzaron Semiconductor aim to refine the design and manufacture of silicon interposers and standardize the process, flows, and process design kits.
2013-05-30 Collaboration to yield low cost interposers for 2.5D ICs
A*STAR Institute of Microelectronics, Qualcomm Technologies and STATS ChipPAC teamed up to address issues related to high volume manufacturing of 2.5D interposers.
2013-01-31 Cisco banks on silicon photonics for 2.5D, 3D ICs
Cisco is one of many firms pushing silicon photonics on 2.5D and 3D chips to lessen the cost of next-generation networks.
2015-05-04 Chip incubator opens start-ups for low-cost power, 2.5D stacks
Silicon Catalyst established three start-ups to provide tools, space and funding for developers of cost-effective integrated analogue power components and 2.5D stacks, and Bluetooth Low Energy ID tag.
2012-02-13 Challenges, opportunities of the 2.5D/3D ecosystem
While opportunities abound, moving to 2.5D/3D manufacturing has posed significant challenges to designing, fabricating, assembling and testing of 2.5D/3D ICs.
2015-06-18 AMD debuts 2.5D high bandwidth memory stack
The Radeon R9 300 series, a high-end graphics card that uses DRAM chip stacks to give more memory bandwidth, is based on AMD's Fiji GPUs and HBM chip stacks from SK Hynix.
2014-06-05 Address SoC routing congestion with 2.5D SiP
The best of both worlds approach that the electronics industry has come up with to solve a design dilemma is the System in Package (SiP) in a 2D package.
2012-12-20 A*STAR offers 2.5D through-silicon-interposer MPW service
The service is aimed at providing a cost-effective platform to do research and development prototyping and proof-of-concept in 2.5D TSI technology.
2012-11-01 TSMC: Quad patterning likely alternative to EUV for 10nm
TSMC's chief technologist stated that quad patterning may be needed for 10nm process technology if extreme ultraviolet lithography is not available by 2015.
2014-09-12 Intel plans to extend Moore's Law to 7nm
Chipmakers generally don't expect the much-delayed extreme ultraviolet lithography in time for 10nm chips, but many still hold out hopes it could be ready for a 7nm generation.
2011-12-23 GSA details 3D IC evolution
The 3D IC architecture report provides further insight on the current state of 3D and 2.5D technology such as the benefits of the technologies.
2012-10-18 ARM's V8 to be used for TSMC's 16nm FinFET
Taiwanese foundry plans to use ARM's first 64bit processor, the V8, as a test vehicle for the 16nm FinFET process.
2013-06-25 A*STAR IME, IC firms team up to tackle industry issues
A*STAR Institute of Microelectronics launched the 2.5D Through-Silicon Interposer Consortium to speed market adoption of TSI tech, which is driven by demands in computer infrastructure and CEs.
2011-09-27 A primer on 3D-IC design challenges
Know the 3D-IC design challenges such as system exploration, floorplanning, analysis, and design for test (DFT), and learn how designs will evolve as 3D-IC goes on to become a necessity for managing power, performance, form factor, and cost goals.
2014-01-16 3D integration leads to robust I/O performance, says IBM
IBM fellow Jon Casey tells EE Times that the semiconductor industry needs to embrace chip stacking amid a slowdown in Moore's Law and the rise of data-driven applications.
2013-11-12 3D IC success hinges on major foundries
3D chip stack technology is real and has users, but not high-volume ones, according to a panel of experts.
2013-07-26 Metrology system configured for advanced packaging
Rudolph Technologies' metrology suite includes specially-designed configurations for wafer level packaging, 2.5D (interposer) and 3D ICs using through-silicon via (TSV) as interconnects.
2014-06-16 Kingyoup bonding equipment addresses miniaturisation
The temporary bonding and de-bonding equipment enables 3D ICs, 2.5D packaging integration and system applications. It promises throughput of over 60 wafers to 100 wafers per hour.
2011-10-28 FPGA boasts 6.8 billion transistors
Xilinx claims an industry-first with the most number of transistors for Virtex-7 2000T by using 2.5D IC stacking.
2015-05-22 Why Moore's Law is nowhere near ready to meet its maker
In 2003, Intel predicted an end to Moore's Law shortly after hitting the anticipated 16nm node, but today it seems we're on track for 10nm fairly soon with 7nm not far off.
2010-05-11 Why electronics industry needs 3D shift
According to Silicon Frontline's Dermott Lynch, the electronics industry needs innovation in 3D extraction technology to move past the limitations of existing solutions.
2012-05-25 UMC begins phase 5 & 6 of Fab 12A
The expansion begins UMC's new generation of 300mm manufacturing that will extend 28nm production and establish a solid foundation for 20nm and beyond to meet customers' high-end demand.
2013-10-11 TU Delft, Imec co-author test flow for 3D IC optimisation
3D-COSTAR aims to optimise the test flow of 3D stacked ICs by compiling the yields and costs of design, manufacturing packaging and logistics.
2011-12-15 TSMC pushes thru with 3D chip
The semicon firm claims its approach will be simpler, cheaper and more reliable, focusing on creating TSVs early in the process, then adding packaging capabilities to its fabs.
2014-04-25 TSMC fleshes out IC line-up with shrunk TSVs
Based on its work on chip stacks, TSMC will launch in July an enhanced version of the 16nm FinFET technology with up to 18 per cent faster data rates and lower leakage, in addition to a planned 10mm and 7mm processes.
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