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| 2013-07-11 | Xilinx tapes out 20nm FPGA device The firm worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process to result in the first tape-out of the ASIC-class programmable architecture: UltraScale. |
| 2013-02-04 | Xilinx expands 20nm design portfolio The 20nm portfolio builds upon the company's breakthroughs proven at 28nm to provide an extra generation of system performance, lower power and programmable system integration. |
| 2014-05-05 | Xilinx 20nm Kintex FPGAs achieve compliance to PCI Express The UltraScale family supporting Gen3 or 8Gbit/s speeds with integrated End-point blocks for PCI Express passed rigorous electrical, protocol, and interoperability tests at the latest PCI-SIG event held recently. |
| 2011-08-23 | Wafer inspection tool targets 20nm device nodes KLA-Tencor has introduced the eDR-7000 e-beam wafer defect review system, an enabling tool for chip manufacturing at the 20nm device nodes and below. |
| 2013-04-05 | TSMC to kickstart 20nm line ahead of schedule TSMC is reportedly poised to start installing equipment for 20nm production at its fab in Tainan, Taiwan, on April 20 enabling it to begin volume production at the end of the second quarter. |
| 2010-04-15 | TSMC skips 22nm, leaps to 20nm half-node Taiwan Semiconductor Manufacturing Co. Ltd announced plans to skip the 22nm "full node" after the 28nm node and move directly to the 20nm "half node." |
| 2012-04-20 | TSMC shifts from multiple to single-only process at 20nm Shang-yi Chiang, EVP at TSMC, said the firm might also offer an 18nm or 16nm process node after 20nm if lithography technology is not available to make 14-nm devices cost effectively. |
| 2012-10-11 | TSMC releases 20nm, CoWoS design reference The silicon-validated CoWoS Reference Flow enables multi-die integration to support high bandwidth, low power and can achieve fast time-to-market for 3D IC designs. |
| 2012-05-02 | TSMC pulls in 20nm, ups capex to $8.5B TSMC said that it needed to increase capex because of stronger than expected demand for 28nm wafers and because it has decided to "pull in" the creation of a 20nm R&D process line. |
| 2012-10-17 | TSMC names EDA partners for CoWoS, 20nm TSMC has validated technologies from Cadence, Mentor and ANSYS for use in its 20nm and CoWoS design infrastructure. |
| 2009-11-19 | Toshiba touts EUV photoresist for 20nm process Toshiba Corp. has developed a photoresist suitable for use with EUV lithography and proved its viability in the first 20nm generation process technology. |
| 2012-05-17 | Tool eases migration to 28nm, 20nm Sagantec's nmigrate layout migration and optimization tool can migrate and DRC-correct cell layout and make sure the layout adheres to all advanced design rules, including coloring for double patterning. |
| 2014-04-08 | Taking a closer look at 20nm bulk CMOS Foundry vendors planned to migrate to 16/14nm FinFETs rather than 20nm bulk CMOS, but the reality of FinFETs is that the present device structures do not give cost competitive products through 4Q17. |
| 2013-09-24 | Synopsys uses TSMC's 20nm SoC process for interface IP The silicon-proven Synopsys DesignWare USB, DDR, PCI Express and MIPI PHY IP on TSMC's 20nm SoC process is designed to achieve high yield by meeting the requirements of advanced manufacturing design. |
| 2011-06-07 | STMicroelectronics completes 20nm chip tapeout The tapeout of STMicroelectronics' first 20nm technology demonstrator test chip has been successfully completed with Synopsys. |
| 2010-06-09 | ST readies 20nm tape out in 2012 STMicroelectronics NV chief technology officer Jean-Marc Chery announced the company will be ready to tape out designs using a 20nm CMOS low-power (LP) process technology in Q4 2012. |
| 2014-10-22 | SK Hynix develops 16GB DDR4 NVDIMM on 20nm class technology SK Hynix' NVDIMM can send DRAM data to NAND Flash whose density is twice that of the DRAM in an unanticipated power loss by combining DRAM, NAND Flash and the module controller in a single module. |
| 2013-04-15 | Samsung outs 128Gbit flash under 20nm Samsung has begun mass production of 128 Gbit NAND flash memory aimed at driving the transition from magnetic to solid-state drives. |
| 2011-01-24 | Samsung launches 20nm technology Designed for logic and foundry applications, Samsung's 20nm process features bulk CMOS technology, 12 metal layers, copper interconnects, ultra low-k, stressors and a high-k/metal-gate scheme. |
| 2014-10-22 | Samsung delivers 8Gbit 20nm DDR4 chips for servers Beyond the 32GB modules, the new 8Gb chips will allow production of server modules with a maximum capacity of 128GB by applying 3D through silicon via (TSV) technology |
| 2013-09-02 | Samsung creates DDR4 using 20nm class process tech The firm's 20nm-class 4Gb DDR4 follows the introduction of 50nm-class 2Gb DDR3 in 2008, culminating in a full-fledged transition to DDR4 for large-scale data centres and other enterprise applications. |
| 2014-03-20 | Samsung announces prod'n of 20nm-based 4Gb DDR3 memory A key element of the latest design and manufacturing technology by Samsung is a modified double patterning and atomic layer deposition that allows for continued scaling. |
| 2014-09-24 | NTT Electronics outs Broadcom-enabled 20nm 100G coherent PHY Broadcom revealed that its high performance 20nm signal processing enhanced mixed signal technologies have enabled NTT Electronics' NLD0640 100G coherent digital signal processor. |
| 2013-07-05 | NAND flash scaling: 20nm node and below Here are some of the fundamental cell design issues considered and addressed to arrive at this planar cell technology. |
| 2010-03-18 | Mentor, ST co-develop 32/20nm design solutions Mentor Graphics Corp. and STMicroelectronics have entered a broad-scoped collaboration to develop advanced design solutions at the 32nm technology node and down to 20nm node. |
| 2013-06-03 | Mentor Graphics, Globalfoundries team up for 20nm kits Mentor Graphics and Globalfoundries recently unveiled a collaboration to deliver 20nm design kits for the Olympus-SoC netlist-to-GDS platform. |
| 2010-12-09 | Magma preps Talus IC implementation tool for 20nm The company claims Talus ver.1.2, a tool for routing, timing and extraction for SoC implementation enables engineers to implement 1 million to 1.5 million cells per day. |
| 2003-01-21 | Lithography leap creates 20nm chip features Scientists at the University of Wisconsin have found a way to create 20nm chip feature sizes with 100nm masks, giving an unexpected leap to Moore's Law and possibly extending the life of current lithography. |
| 2012-09-26 | Intel aims to steamroll competition beyond 20nm Despite ARM's current lead in low power processing, Intel believes that it will eventually surpass them as they continue to advance their process technology. |
| 2013-06-25 | Imec creates dielectric to scale NAND flash below 20nm Researchers from Imec have created a dielectric that is scalable in thickness, making the material promising for further scaling of 2D NAND flash memory below 20nm. |
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