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2013-01-31 Open ecosystem team up spawns 3D IC
STATS ChipPAC and UMC unveiled a 3D chip stack, consisting of a Wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip, which boasts package-level reliability success.
2011-12-21 JEDEC to release 3D IC standard
JEDEC will release in late December or early January 2012 the first 3D IC interface standard
2008-06-10 IBM splashes water on hot 3D chips
IBM's Zurich recently demonstrated 3D chip stacks that are cooled with water. The team predicted high-end IBM multicore computers will migrate from the copper-plate water-cooling method to the 3D chip-stack in five to 10 years.
2013-03-28 3D stacking is the future of chip design, says Xilinx
Xilinx's Liam Madden says it is time to move on from Moore's Law with 3D integration as the standard for chip design
2013-11-12 3D IC success hinges on major foundries
3D chip stack technology is real and has users, but not high-volume ones, according to a panel of experts.
2005-05-02 ZyCube duo has big plans for 3D circuits
Two executives from Zycube Co. Ltd lay the road map for significant trends in 3D technology
2008-08-13 World's first 3D chip technology surfaces
The world's first 3D chip process is ready for licensing from the fabless semiconductor design house BeSang
2015-04-15 SRC to standardise 3D chip testing
Duke University lays down the plan to designing-for-test the TSVs, so that large inexpensive probes can touch many TSV microbumps simultaneously to take measurements that ensure defect-free stacked die.
2015-07-21 Semicon West highlights 10 chip trends
During the recent Semicon West, executives from a number of chip companies discussed the ongoing developments on semiconductors technology
2009-03-23 Nanorods simplify 3D chip stacking
Interconnecting bare die to form 3D chip stacks is best done through low-temperature wafer bonding before dicing, according to Rensselaer Polytechnic Institute researchers, who described how to perform the process with nanoscale copper rods
2015-03-27 Micron, Intel tout 3D NAND flash chips
Micron and Intel developed their own 3D NAND flash chips, which will sell as chips and in solid-state drives. It will pack 256Gbits into vertical NAND chips using MLC and 384Gbits in TLC versions
2012-03-28 Micron advances with 3D chips
The company has laid down its plans with the Hybrid Memory Cube that is currently being backed by Altera, OpenSilicon, Samsung, Xilinx and IBM.
2010-03-17 Microfluids cool down 3D IC stacks
IBM Researchers, in collaboration with two Swiss partners, seek to extend Moore's Law another 15 years using 3D stack architectures with liquid-cooling microchannels
2015-11-17 ISSCC to see advancements in vision processors, 3D chips
Samsung is set to unveil its 10nm process technology and enhancements in its SRAM, DRAM and flash technologies while Mediatek will showcase a 10-core CPU, featuring three ARMv8a CPU clusters.
2013-06-20 Intel touts eDRAM as forerunner to 3D ICs
Intel's eDRAM technology is expected to challenge discrete graphics sockets in high-end notebooks and servers.
2011-04-06 Industry pushes TSV-based 3D chips development
Amid fears that IC scaling is becoming too costly for chipmakers, the IC industry is working to develop TSV-based 3D chips, and stack and connect devices in a 3D configuration using TSVs
2009-10-06 IMEC pushes 3D integration of DRAM on logic
IMEC and its 3D integration partners have prototyped a DRAM chip integrated on top of a logic IC
2012-12-14 IBM showcases 3D server chip stacks
IBM has showcased its techniques for stacking 45nm processors at IEDM. The company's techniques could give the processors significant performance and power gains.
2007-06-01 IBM gets on the road to 3D packaging
News that IBM Corp. this year will sample its first commercial devices to make direct metal connections between chips marks a small but significant milestone on the road to 3D packaging
2013-04-04 Globalfoundries delays 3D IC stack production
The company says it expects to use the 20nm process for 3D chips that may not ship in volume until 2015 or later
2011-06-16 FEI ion beam cuts imaging time for MEMs, 3D chips
The Vion PFIB tool can cut the time to image MEMS and 3D chip features by 20x, from more than 10hrs to under 40mins for TSVs, revealing in minutes chip features ranging in size from 30nm to 1mm
2007-10-25 EDA's big three unready for 3D chip packaging
Without design tools to allow exploration and tradeoffs to be made in 3D layouts, engineers are restricted to design in two dimensions and occasionally stack chips crudely. But without a clear market for 3D design EDA vendors are unlikely to offer tools
2007-06-25 Designing in the age of 3D systems
The optimal utilization of the third dimension requires a careful design of the overall 3D system architecture
2014-03-20 Chip stacks feature near-zero TSV keep-out zones
GlobalFoundries describes a middle-of-line layer stack technique that uses nitride, PMD oxide, and a contact protection layer with a high coefficient of thermal expansion
2012-03-09 A*STAR, Applied Materials unveil 3D chip packaging R&D center
The new facility positions Singapore as a global leader in semiconductor R&D and is expected to help accelerate the development and adoption of 3D packaging technology globally
2014-05-08 3D chip-making technique utilises metallisation layers
The technique fabricates active devices interleaved between the metallisation layers atop a standard CMOS die, eliminating the expense of vertically stacked transistors or of stacking dies with TSVs.
2011-12-14 3-chip stack combines DRAM, SoCs
As an effort to push 3D integration, engineers used TSVs to link a wide I/O DRAM and two identical multicore SoCs in a device that can support 12.8GB/s of memory bandwidth
2012-02-06 TSMC to roll 3D IC assembly service next year
The company has one year to get all physical design kits and EDA support in place to allow customers to design with COWOS, the technology standing for chip on wafer on substrate
2005-10-20 STATS ChipPAC wants to be 3D king
Nearly two years after the big merger, Singapore's STATS ChipPAC Ltd is treading slightly above stormy waters in the competitive chip packaging and test market
2013-08-07 Samsung embarks on 3D V-NAND mass production
Samsung has begun mass producing 3D vertical NAND flash memory designed for range of application including embedded storage and SSDs
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