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2014-08-26 Memory process roadmap soldiers on amid looming 3D tech
The constant reduction in feature sizes used to make ICs has improved memory-chip performance by increasing per-chip storage capacities, lowering power consumption, and improving data storage speed
2013-07-29 Making 3D NAND flash practical
Learn about the key features and benefits of SMArT scheme which is touted to open the 3D NAND flash era
2015-10-22 Intel reveals $5.5B-plan to build 3D NAND in China
The company said the first production of 3D NAND for its solid state drives at the fab, located in the Northeast China city of Dalian, is forecast to start in 2H16
2013-01-24 Imec, Cadence team up for DFT solution for 3D memory
Cadence's and imec's solution includes generation of DRAM test control signals in the logic die and inclusion of the DRAM boundary scan registers test access mechanisms of the 3D test architecture
2011-10-14 IBM, 3M partnering for 3D ICs
IBM Corp. and 3M Corp. are collaborating on developing the first adhesives that can be used to package semiconductors into densely stacked silicon "towers."
2011-12-12 Gesture recognition: Leading toward 3D UIs
Read about the challenges in gesture recognition in 3D interaction and the techniques to overcome them in embedded systems
2014-07-08 Deposition, etch equipment revs up 3D NAND ramp-up
The equipment from Lam Research addresses the need for three of the most critical steps in forming 3D NAND memory cells: stack deposition, vertical channel etching, and tungsten wordline deposition
2012-02-03 Advances in 3D-IC testing
Read about the design-for-3D-test architecture and implementation flow developed by researchers at Industrial Technology Research Institute based on the Synopsys test solution
2011-09-27 A primer on 3D-IC design challenges
Know the 3D-IC design challenges such as system exploration, floorplanning, analysis, and design for test (DFT), and learn how designs will evolve as 3D-IC goes on to become a necessity for managing power, performance, form factor, and cost goals
2008-09-01 3D-TSVs spark packaging revolution
Chips face the so-called "More-than-Moore" 3D integration route in order to pursue the continued aggressive scaling demanded by the historical law. 3D integration with through-silicon vias (3D-TSV) will accelerate the consolidation happening in CMOS wafer fabs and the shift toward the fabless foundry model
2010-06-18 3D TSV chips not ready for prime time
Some experts at the International Interconnect Technology Conference (IITC) concluded that 3D chips based on through-silicon-vias (TVS) are not ready for prime time
2013-12-05 3D NAND industry-wide adoption still shaky
Development and production of 3D NAND is ramping up, but 2014 will clearly be a shakeout year
2010-07-16 3D chip standard talks start at Semicon West
Participants of a Semicon West 2010 workshop took the first crack at outlining standards for 3D silicon chips to address design, yield and cost problems
2011-12-14 3-chip stack combines DRAM, SoCs
As an effort to push 3D integration, engineers used TSVs to link a wide I/O DRAM and two identical multicore SoCs in a device that can support 12.8GB/s of memory bandwidth
2007-12-17 Chip-on-MEMS' enables wafer-level calibration
A new technique called "chip-on-MEMS" bonds ASIC dice atop an entire MEMS wafer before dicing, according to developer VTI Technologies
2003-01-29 Xanoptix stacks chips to create hybrid ICs
Startup Xanoptix Inc. has developed a wafer-scale manufacturing process that allows silicon die, optical semiconductors, and compound semiconductors such as GaAs and InP chips to be stacked into 3D structures to create hybrid ICs
2006-08-03 SiP tech stacks logic, gigabit-class memory in one package
NEC Corp., NEC Electronics Corp. and NEC Electronics America Inc. unveiled a new system-in-package technology capable of stacking logic and gigabit-class memory in a single package.
2014-03-28 On-chip interconnect costs head for further study
With 16nm chips moving to production this year, companies are actively developing the 10nm and 7nm technology nodes.
2013-04-15 TSMC FinFET production set in 2013
Company executives detailed the new processes and how they aim to get there and also gave an update on 3D chip stacks and their on-going ramp of today's 28nm process node.
2012-02-24 Integrated voltage regulators cut power by 20%
Inverted voltage regulation will be able to respond to the energy needs of future CMOS chips in nanoseconds, compared to microseconds with off-chip voltage regulators, the researchers said
2012-05-02 Globalfoundries preps for 20nm TSVs
If all goes well, the company hopes to take production orders in the second half of 2013 for 3D chip stacks using 20nm and 28nm process technology.
2012-03-15 Electronics firms clamour for more collaboration
Executives of Cadence, TSMC and ARM are calling for other companies to step up their collaborations to deal with the growing complexity of technologies of semiconductor design.
2013-12-30 Altera CEO: Industry is looking up despite down 2014
John Daane, Altera's CEO, stated that Moore's Law will remain while the near term looks upbeat as a result of scaling that will continue for several generations, offsetting rising fab costs.
2007-11-28 Rambus shows alternative way to terabyte memory
Rambus has developed technologies that could enable links to memory chips delivering up to a terabyte per second and could provide a lower-cost alternative to 3D chip stacking
2011-10-11 Price challenges hinder TSV adoption
In order for chip stacks using high density through-silicon vias (TSVs) to be used in high volume devices, major price adjustments should be done
2012-05-10 Microsoft joins memory consortium
Microsoft's participation signals the potential of the Memory Cube to drive changes in the traditional memory hierarchy and systems software for computers and networks.
2014-11-04 The lowdown on manufacturing RRAM
Resistive memory technologies involving simple two-terminal devices can be incorporated into backend metal layers to provide an elegant solution for meeting density, capacity and cost challenges.
2005-06-23 Stacked package from Sharp allows 0.5-mm grid
Sharp Corp. has developed packaging technology that allows stacking of multiple packages with 0.5mm pitch ball grids, which the company claims is the industry's tightest pitch.
2008-10-01 Stacked microprocessor system promises better performance
Take a different approach to chill. A group of researchers just did, resulting in what may be the most efficient heat dissipation possible for stacked microprocessors.
2010-06-21 Sematech welcomes Qualcomm as first fabless member
Qualcomm Inc. has joined chip-making consortium Sematech to gain an edge in next-generation technology, reportedly including 3D chips
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