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2008-06-06 Will 3D through-silicon vias break into mainstream
The 3D technology based on through-silicon vias technology took center stage at the IEEE 2008 International Interconnect Technology Conference but there is still no consensus just how the industry will bring the long-awaited technology into the mainstream
2012-06-15 TI describes 28nm CMOS TSV integration
A paper by TI researchers showed results indicating minimal effect on transistors within 4 microns of TSV placement.
2009-10-01 SUSS MicroTec joins ITRI 3D consortium
The Advanced Stacked-System Technology and Application Consortium will implement SUSS MicroTec's 300mm technology.
2012-10-11 SPTS signs JDP with Fraunhofer for 300mm 3D IC Apps
The program will use 300mm APM plasma enhanced chemical vapor deposition modules installed on a Versalis platform alongside SPTS etch chambers in the ASSID centre in Germany.
2009-07-16 Soitec, IBM pioneer 22nm for 3D ICs
Soitec Group and IBM Corp. have teamed up to pioneer 22nm node silicon wafer substrate and bonding techniques that will enable wafer-level, 3D integration technology for next-generation ICs.
2009-12-04 Soitec, CEA-Leti push 3D integration
The Soitec Group and CEA-Leti will offer comprehensive industrial solution beginning with process customization for prototype demonstration and will include licensing, both in 200mm and 300mm.
2013-06-03 Si2 set to unveil PDN Standard for 3D integrated ICs
The 3D IC Design Exchange Format Standard for Power Distribution Networks describes a unified interface protocol for both Power/Ground and signal ports for die-2-die and package-2-PCB interfaces
2015-07-27 Semicon West highlights path towards 3D IC
The recent event underlined the significance of the move towards more advanced 3D IC technology, as well as the impact of the 'More than Moore' leading to this progress
2011-11-09 Sematech starts 3D tech forum
Sematech has launched an online forum to promote the development of standards for heterogeneous 3D integration.
2011-12-22 Sematech details 3D IC tech hurdles
Sematech has identified heterogeneous computing, memory, imaging, smart sensor systems, communication switches and power delivery/conditioning as some of the potential future killer applications
2011-10-19 Recent developments in 3D integration
Here's a discussion on through-silicon via and mechanically flexible interconnect, and how these are being currently developed.
2009-03-11 R3Logic to advance 3D design flow R&D
R3Logic announced that it has created a new R&D center in Grenoble, France to develop and enhance its design tools for 3D heterogeneous system and system-in-package design
2008-07-16 Qualcomm, IMEC team on 3D tech for wireless apps
Qualcomm announced it is the first fabless IC firm to participate in IMEC's industrial affiliation program (IIAP) on 3D integration.
2014-06-18 Qualcomm advocates monolithic 3D adoption
The chipmaker appears to be making a concentrated effort to employ 3D integration technology to stretch out the semiconductor roadmap beyond the scaling trajectory predicted by Moore's Law.
2010-03-22 Novellus, IBM launch 3D TSV program
Novellus Systems and IBM Corp. are opening a joint development program to design a manufacturing-worthy, copper-based, 3D semiconductor through-silicon via (TSV) process
2013-12-18 Monolithic 3D ICs gain momentum
A number of companies have, in one way or another, started to take leverage in the monolithic 3D IC space and designated the technology as an alternative to dimensional scaling
2015-10-14 Laying down the scaling path for monolithic 3D
The IEEE S3S 2015 provided comprehensive coverage of R&D activities in the monolithic 3D space such as integrating a monolithic 3D device without changing the existing frontline fab process
2013-04-23 Interposers to dictate the future of 3D chip stacks
The market for silicon interposers will grow by 88 per cent annually through 2017 with all the big semiconductor makers looking to grow their 3D integration capabilities.
2015-03-06 Intel recommends 2.5D, 3D integration for next-gen chips
Intel emphasised that heterogeneous integration enabled by 3D IC is essential to the development of future SoCs, especially in terms of scaling lithography processes.
2011-04-06 Industry pushes TSV-based 3D chips development
Amid fears that IC scaling is becoming too costly for chipmakers, the IC industry is working to develop TSV-based 3D chips, and stack and connect devices in a 3D configuration using TSVs
2013-08-30 Imec, Entegris team up on 3D wafer handling
The organisations are working on a solution to safely transfer and handle multiple kinds of 3D IC wafers without the risk of breakage and other damage that may occur during the 3D production process
2011-05-26 Imec, Atrenta develop exploration flows for 3D ICs
Atrenta and Imec have co-developed a design flow for heterogeneous 3D stacked ICs
2009-10-06 IMEC pushes 3D integration of DRAM on logic
IMEC and its 3D integration partners have prototyped a DRAM chip integrated on top of a logic IC.
2011-05-27 IMEC extends 3D research agreement with Qualcomm
IMEC and Qualcomm will continue to be partners in researching for and designing advanced technologies related to 3D technology
2012-12-14 IBM showcases 3D server chip stacks
IBM has showcased its techniques for stacking 45nm processors at IEDM. The company's techniques could give the processors significant performance and power gains.
2011-03-14 Hynix supports Sematech 3D interconnect program
By joining the 3D Interconnect program, Hynix hopes to help accelerate the commercialization of wide I/O DRAM and realize 3D's potential as an affordable path to IC production growth
2015-04-07 Future of 3D SoCs: Adding unlimited layers sans TSVs
The future of three-dimensional (3D) very large scale integration (VLSI) for system-on-chips (SoCs) will not stack die connected by through-silicon-vias (TSVs), but will build them on a single layered die, according to Qualcomm.
2006-05-31 FlipChip, Engent to develop 3D wafer level CSP tech
FlipChip and Engent announced an alliance aimed at accelerating the development and deployment of 3D wafer level CSP technologies for stacked die packaging applications
2011-06-16 FEI ion beam cuts imaging time for MEMs, 3D chips
The Vion PFIB tool can cut the time to image MEMS and 3D chip features by 20x, from more than 10hrs to under 40mins for TSVs, revealing in minutes chip features ranging in size from 30nm to 1mm
2015-07-03 Examining 3D embedded substrate power packaging
Here is a look at 3D embedded substrate power packaging technologies, which will be increasingly deployed in everything from cell phones to hybrid electric vehicles
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