Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > 3D layout

3D layout Search results

?
?
total search129 articles
2007-10-25 EDA's big three unready for 3D chip packaging
Without design tools to allow exploration and tradeoffs to be made in 3D layouts, engineers are restricted to design in two dimensions and occasionally stack chips crudely. But without a clear market for 3D design EDA vendors are unlikely to offer tools
2010-05-11 Why electronics industry needs 3D shift
According to Silicon Frontline's Dermott Lynch, the electronics industry needs innovation in 3D extraction technology to move past the limitations of existing solutions
2001-07-16 Validate EMC design rules with 3D simulation
This article provides an overview of EMC- and 3D-analysis tool capabilities that can enhance an your design's performance
2014-03-26 T-bone enables board for 3D printing
The T-bone, which utilises an Cortex A8 microcontroller, allows expanded usage of the host's, BeagleBone, resources by offloading the complex motion control processing functions.
2015-08-31 Storage array packs 3D NAND drives
By supporting 3D TLC SSDs, Kaminario's K2 v5.5 customers can double the effective capacity of the array to more than 360TB per K-block and scale one K2 array to multiple petabytes in a single rack unit
2007-11-28 PCB/FPGA design goes 3D with Altium tool
The Altium Designer 6.8 with new 3D PCB visualization capability allows designers to see at any time exactly how the manufactured board will look
2010-06-22 Layout visualization platform packs route trace function
From TOOL Corp. comes the LAVIS Version 10.0 layout visualization platform software integrated with route trace function
2007-05-02 Layout viewer serves trillion transistors
Micro Magic claims that its Max-View GDSII layout viewer provides instantaneous viewing at any zoom level of chips with up to 1 trillion transistors
2002-11-07 Layout tool polishes designs for improved IC yields
Xyalis has developed a layout finishing tool that determines where dummy tiles can be placed in a chip design to increase manufacturing yields
2011-12-21 JEDEC to release 3D IC standard
JEDEC will release in late December or early January 2012 the first 3D IC interface standard
2001-03-01 Integrating PCB layout with mechanical design
Learn how you can save time and reduce the potential for errors by putting the Intermediate Data Format to work on your next design project.
2006-12-05 GenISys layout tool speeds MEMS design
GenISys has started sampling a flexible simulation platform for mask aligner lithography that lets them virtually model, redesign and optimize device layouts and processes in hours rather than weeks.
2011-11-16 Embedded die tech-based 3D package unveiled
ChipletT and ChipsetT enable packaging in the sub-250?m range, up to 50 percent less than alternative embedded die solutions, the companies claimed.
2011-05-23 EDA supplier claims industry's first hierarchical 3D extractor
Complementing top EDA vendors' design flows, H3D is an accurate 3D extractor that runs with sub-linear performance and delivers a hierarchical output that enables post-layout simulation speed up.
2014-01-22 Develop sense electrodes for 3D touchpad surfaces
Know the most important design choices that need to be made when designing a touchpad for a 3D surface
2011-12-08 Designing 3D-ICs (Part 2
Here's the second instalment of this series that tackles the tools that can be used to handle a complete backend flow, and enable true 3D design partitioning, synthesis, placement, and routing
2011-12-07 Designing 3D-ICs (Part 1
Learn about the tools that can be used to handle a complete backend flow, and enable true 3D design partitioning, synthesis, placement, and routing
2013-02-01 An assessment of PCB layout tools
The selection of the right tool for the layout should be at the forefront of PCB layout planning and must never be ignored
2008-06-05 Altium enables 3D design without guesswork
The folks at Altium have introduced technology that they say, for the first time, lets electronic designers fit their boards into enclosures in real time, in 3D, without guesswork
2007-08-31 Agilent develops 3D electromagnetic simulator
Agilent Technologies has developed Momentum GX, a planar 3D electromagnetic simulator designed to expand the accuracy and range of passive circuit libraries, including parasitic models and entire circuits
2011-09-27 A primer on 3D-IC design challenges
Know the 3D-IC design challenges such as system exploration, floorplanning, analysis, and design for test (DFT), and learn how designs will evolve as 3D-IC goes on to become a necessity for managing power, performance, form factor, and cost goals
2008-08-20 3D EM simulation solution rolls for RF module design
Agilent Technologies Inc. has developed the EMDS-for-ADS, an integrated design flow solution that includes full 3D electromagnetic (EM) simulation for RF Module Design
2015-09-17 Spot IGBT degradation through power cycling
Here is a look at an experiment in which we conducted thermal transient tests from one steady-state to another to determine cause of failure for a small sample of IGBTs.
2007-05-01 Sigrity tool automates decap selection
Sigrity Inc. claims a breakthrough with its tool that helps automate the selection and placement of decoupling capacitors.
2010-07-07 PCB design tool offers video tutorials
RS Components has launched the DesignSpark design environment that features DesignSpark PCB, a PCB drawing and layout tool that comes with a unique range of functions and features
2008-05-01 Partition and package to miniaturize handsets
Designers are turning to system-in-package, 3D IC stacking and wafer-level packaging to enable the acute miniaturization found in handsets, particularly for RF functions
2003-05-23 OEA upgrades spiral inductor synthesis
OEA Int'l Inc. is claiming a major upgrade for Spiral, a 3D toolset for synthesizing embedded spiral inductors in analog and RF chips, hybrids, multichip modules, and PCBs
2001-04-15 Multichip DRAMs serve graphics apps
No technology can last forever. So the question arises: how long can multichip package solutions last in the diverse and rapidly changing graphics market?
2002-06-28 Motorola adopts Cadence's analog/mixed-signal design solution
Motorola Inc. has adopted Cadence Design Systems Inc.'s full-chip 3D device-level parasitic extraction solution called Assura RCX, for its analog and full-custom design flows
2004-08-02 Mixed-signal simulation tool supports Linux
Silvaco's mixed-signal simulator, RC inductance extractor and soft-error modeling tool all support Linux under a new GUI.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top