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2009-07-16 Soitec, IBM pioneer 22nm for 3D ICs
Soitec Group and IBM Corp. have teamed up to pioneer 22nm node silicon wafer substrate and bonding techniques that will enable wafer-level, 3D integration technology for next-generation ICs.
2013-10-23 SMIC opens R&D, manufacturing facility for 3D ICs
By rolling out a centre dedicated to vision, sensors, and 3D IC, SMIC is hoping to let the world know of its ability to extend its manufacturing and R&D capabilities.
2009-09-02 Nanowire crystals produce 3D ICs
Scientists have developed a process for transforming an amorphous germanium layer into a perfect crystal.
2013-12-18 Monolithic 3D ICs gain momentum
A number of companies have, in one way or another, started to take leverage in the monolithic 3D IC space and designated the technology as an alternative to dimensional scaling.
2013-06-20 Intel touts eDRAM as forerunner to 3D ICs
Intel's eDRAM technology is expected to challenge discrete graphics sockets in high-end notebooks and servers.
2011-05-26 Imec, Atrenta develop exploration flows for 3D ICs
Atrenta and Imec have co-developed a design flow for heterogeneous 3D stacked ICs.
2011-10-14 IBM, 3M partnering for 3D ICs
IBM Corp. and 3M Corp. are collaborating on developing the first adhesives that can be used to package semiconductors into densely stacked silicon "towers."
2011-12-08 Designing 3D-ICs (Part 2)
Here's the second instalment of this series that tackles the tools that can be used to handle a complete backend flow, and enable true 3D design partitioning, synthesis, placement, and routing.
2011-12-07 Designing 3D-ICs (Part 1)
Learn about the tools that can be used to handle a complete backend flow, and enable true 3D design partitioning, synthesis, placement, and routing.
2013-01-31 Cisco banks on silicon photonics for 2.5D, 3D ICs
Cisco is one of many firms pushing silicon photonics on 2.5D and 3D chips to lessen the cost of next-generation networks.
2013-03-21 Nvidia takes on Intel, ventures into business apps
Nvidia unveiled a roadmap that will focus on merging graphics, ARM cores and memory using FinFETs and 3D ICs at it goes head to head with Intel and AMD.
2013-07-26 Metrology system configured for advanced packaging
Rudolph Technologies' metrology suite includes specially-designed configurations for wafer level packaging, 2.5D (interposer) and 3D ICs using through-silicon via (TSV) as interconnects.
2013-12-13 Latest developments in 3D IC technologies
Here's a look at the various forms of 3D IC technology, starting with the simpler incarnations and culminating in today's start-of-the-art implementations.
2012-08-09 Improve SoC yields with diagnostic and repair tools for embedded memory
Learn about embedded memory test solutions, including fault detection in very deep submicron technologies, repair at the manufacturing level, as well as diagnosis for process improvement and field repair capabilities.
2013-12-30 Exploring monolithic 3D IC technologies
Learn about a relatively new approach that seems really promising: the Monolithic 3D IC technology.
2014-01-22 Besi, Imec partner on thermocompression for 3D IC bonding
Imec and Besi have announced that they are collaborating to develop a thermocompression bonding solution for narrow-pitch die-to-die and die-to-wafer bonding with high accuracy and high throughput.
2013-10-24 Xilinx, TSMC announce CoWoS 3D IC volume production
The programmable Virtex-7 HT family claims to be the industry's first heterogeneous 3D ICs in production that feature up to sixteen, 28Gb/s and seventyCtwo, 13.1Gb/s transceivers.
2014-05-28 Wafer-to-wafer bonding pulls off sub-micron accuracy
The sub-micron accuracy was achieved using Ziptronix's technology and EVG's equipment. This approach can be used to manufacture fine-pitch 3D ICs for stacked memory and SoCs, and image sensors.
2011-10-14 The move toward 3D chips
Semiconductor fabrication is moving toward 3D ICs and by next year, 3D chips will be available for commercialization.
2014-06-16 Kingyoup bonding equipment addresses miniaturisation
The temporary bonding and de-bonding equipment enables 3D ICs, 2.5D packaging integration and system applications. It promises throughput of over 60 wafers to 100 wafers per hour.
2012-02-13 Challenges, opportunities of the 2.5D/3D ecosystem
While opportunities abound, moving to 2.5D/3D manufacturing has posed significant challenges to designing, fabricating, assembling and testing of 2.5D/3D ICs.
2011-06-28 3M opens innovation center in Taiwan
3M's application laboratory in Yangmei, Taiwan will provide support for 3D ICs and ultra-thin wafer handling for the semiconductor industry.
2014-01-20 3D IC market predicted to reach $7.52B in 2019
Up from $2.40 billion in 2012, the global market for 3D ICs will log a CAGR of 18.1 percent in 2019, according to Transparency Market Research.
2002-11-15 3D IC design promises to boost chip performance
IBM Corp. has developed a new technique for building 3D ICs that will help increase chip performance, functionality, and density.
2014-03-11 Xilinx: 16nm multi-core chips in the works
Xilinx said it will integrate the future 16nm chips with its own UltraScale architecture, which was first featured in the previous 20nm chips.
2013-07-11 Xilinx tapes out 20nm FPGA device
The firm worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process to result in the first tape-out of the ASIC-class programmable architecture: UltraScale.
2014-03-13 Xilinx rolls out OTN reference designs
The reference designs promise to give customers single-chip solutions for 4x100G OTN transponder and 200G OTN switching applications.
2013-03-06 Xilinx fills ASIC, ASSP gaps for data centres
Incorporating both SmartCORE IP and ARM processor-based smarts with All Programmable devices, the IP targets networks for LTE and LTE Advanced wireless HetNets, and 400G and Nx100G OTN.
2008-08-13 World's first 3D chip technology surfaces
The world's first 3D chip process is ready for licensing from the fabless semiconductor design house BeSang.
2015-09-11 Upcoming IEEE conference to focus on key IoT tech
The emerging IoT market is looking for older nodes with lower development costs, broad range of process options, with many more players both at the foundry side and the design side.
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