Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > 3d-sip

3d-sip Search results

?
?
total search4 articles
2005-10-21 Packaging conference to explore 3D, SIP
Building on the first International Wafer-Level Packaging Congress (IWLPC) event, the second IWLPC conference will explore three-dimensional (3D) chip-packaging and other technologies.
2005-06-23 Stacked package from Sharp allows 0.5-mm grid
Sharp Corp. has developed packaging technology that allows stacking of multiple packages with 0.5mm pitch ball grids, which the company claims is the industry's tightest pitch.
2003-03-10 Sharp, Amkor to develop unified stacked package design
Sharp Corp. and Amkor Technology Inc. have agreed to unify the design for 3D system in package assembly that enables the stacking of very thin packages.
2015-06-10 Altera touts next-gen high-end programmable logic devices
The Stratix 10 FPGAs and SoCs leverage Altera's HyperFlex FPGA fabric architecture built on the Intel 14nm Tri-Gate process to provide 2X higher core performance over previous generation FPGAs.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top