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2006-05-11 KPIT Cummins adopts Cadence AMS kit
The Indian arm of Cadence announced that KPIT Cummins has adopted its AMS Methodology Kit to help its analog mixed-signal designers simplify the application of Cadence technology.
2006-04-28 Cadence AMS kit adopted by non-volatile memory supplier
Cadence announced that Saifun Semiconductors has adopted Cadence's Analog Mixed Signal Methodology Kit
2011-06-03 Simulation products support TSMC's AMS reference
Magma Design Automation announced that TSMC has validated the Titan Mixed-Signal and FineSim simulation products for Analog/Mixed-Signal (AMS) reference
2005-12-15 Methodology kit addresses wireless design challenges
Cadence announced its RF Design Methodology Kit, which is designed to address key challenges in wireless design
2006-02-13 Mentor releases new design kits for Intel's IBIS 4.1 AMS models
Mentor Graphics announced the release of the ICX and ICX Pro Signal Integrity design kits for Intel's next generation I/O controller hub. These kits are said to be the first to utilize Intel's new IBIS 4.1 and IEEE 1076.1 standard VHDL-analog/mixed-signal models.
2006-04-19 Cadence, SMIC co-develop AMS reference flow
Cadence and SMIC jointly developed an analog mixed-signal reference flow to address the needs of designers developing ICs for the consumer, networking and wireless markets.
2002-09-25 Cadence qualifies as prime EDA vendor for AMS
austriamicrosystems has qualified Cadence Design Systems Inc.'s analog/mixed-signal solutions as a reference flow.
2005-09-15 Cadence offers shorter AMS design cycle
The AMS Methodology Kit from Cadence promises to enable analog mixed-signal designers of wireless, wired and consumer electronics devices to achieve shorter, more predictable design cycles while creating reusable AMS blocks.
2003-05-26 austriamicrosystems kit based on Mentor Graphics' design flow
The company has announced the extension of its design environment support that is based on Mentor Graphics' IC design flow.
2013-10-17 Ams reveals method for Li cell monitoring, balancing
The architecture has been implemented in the AS8506 to perform distributed cell monitoring and balancing operations for stacked cell modules, including SOA check and passive or active cell balancing.
2004-09-27 Altera kit empowers engineers using Mentor tool
Mentor announced the availability of the Altera Stratix GX design kit for ICX
2002-04-01 Chartered, Cadence partner in design kit offering
Cadence Design Systems Inc. and Chartered Semiconductor Mfg have collaborated to help the mixed-signal market reduce cycle times on designs using Chartered's foundry process design kits.
2015-12-04 Ultrasonic water flow metering chip works up to 20 years
The TDC-GP30-F01 from Ams is a complete hardware and firmware measurement solution for cold water metre that draws 8.5?A continuous current when capturing flow measurements at 8Hz
2007-06-28 TSMC, Cadence team on 65nm wireless design flow
Cadence and TSMC have teamed on nanometer wireless design and produced a new TSMC 65nm RF PDK compatible with the new Cadence Virtuoso custom design platform.
2003-06-27 Tower PDKs simplify design environments
Tower Semiconductor Ltd. and Cadence Design Systems have announced the availability of the TSL018 and TSL035 foundry-level Process Design Kits that eliminate the need for users to create their own "views" of the Tower technologies in their design environments.
2011-01-21 PDK and reference flow for 0.18um power management process
Tanner EDA and TowerJazz announce PDK for 0.18um power management process. Kit includes symbol libraries for schematic capture software as well as parameterized layout generators for L-Edit
2014-12-26 Optical sensors provide touchless detection
The TMG399x devices from ams feature six key sensing functions such as gesture detection and Mobeam barcode emulation geared for smartphones, tablets and other consumer electronics
2015-10-01 LED light, sensors to enable next-gen medical devices
ams developed the sensing solutions to fill the future market needs, which means a move from today's dumb LEDs to complete spectrally-cognitive sensor platforms and boost IoT deployment
2006-11-16 Design RFICs with greater speed, accuracy
In RFIC design, a "meet-in-the-middle" approach balances top-down fast design processes with bottom-up silicon accuracy to produce a predictable schedule, leading to first-pass silicon success.
2004-05-04 Mentor Graphics, X-Fab roll out three TDKs
Mentor Graphics and X-Fab have announced the first three in a series of technology design kits supporting X-Fab's CMOS process technologies.
2007-06-22 Cadence aids HHNEC in first 0.18?m EEPROM PDK
Cadence Design Systems announced that Hua Hong NEC Electronics has developed its first 0.18?m process design kit using Cadence's PDK automation system
2015-04-30 Taking advantage of TSMC's 28HPC process
Here are five areas where designers can take advantage of this new process with logic library technology to optimise the performance, power and area of their system on chips.
2010-08-31 MIMO test simulates varying radio patterns
The RF environment simulator is a test system for MIMO OTA that allows repeatable measurement of radiated performance of wireless devices in a simulated multi-path environment.
2005-10-10 Mentor making automotive EDA push
Looking to push its widely acknowledged lead in the automotive EDA space, Mentor Graphics Corp. Thursday (Oct. 6) announced a major new automotive design push.
2005-03-16 Gbit contender enters ultrawideband fray
Challenging established UWB powerhouses, Pulse-Link has announced details of its own UWB architecture and formed an alliance to promote it.
2006-08-01 EDA&T-Taiwan showcases latest in EDA, test
To update engineers on the latest developments in EDA and test, the 14th Annual EDA & Test Taiwan Conference & Exhibition will gather the world's top vendors on August 17-18 at the Taipei International Convention Center.
2007-02-01 Circuit designer takes control over LOD parameters
The circuit designer would like circuit simulation to match post-layout simulation as closely as possible to avoid changes necessitated by differences in device operation between the schematic and layout.
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