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2002-08-28 | Xilinx overhauls FPGA software design package A major upgrade of Xilinx Inc.'s Integrated Software Environment FPGA design tool package features new system-level design capabilities, improved performance, and new utilities to simplify FPGA design |
2007-12-12 | Vitesse ups investment in India design center Vitesse Semiconductor Corp. plans to significantly increase its foothold in Hyderabad, India by increasing its investment in this design center by over 100 percent per year over the next three years |
2003-07-02 | ViewAhead embedded SoC solution based on ASIC platform Designed for OEM manufacturers, the ViewFleX500 embedded SoC solution from ViewAhead Technology reduces development costs and time-to-market for imaging devices. |
2003-12-16 | Using ISSP technology in structured ASIC design NEC's ISSP technology for designing structured ASIC has become popular with design engineers because of its easy-to-use design flow and clear road map for 90nm. |
2006-08-11 | TSMC increases investments in local design house, sensor foundry Taiwan Semiconductor Manufacturing Co. Ltd has separately increased its investments in two Taiwanese companiesGlobal Unichip Corp. and VisEra Technologies Co. Ltd. |
2000-08-31 | Translation of existing ASIC designs This application note describes the types of data required from the ASIC user and the process steps followed by Atmel to successfully translate an existing ASIC design, and presents the results of two translation efforts. |
2004-12-21 | Toshiba supports Cadence RTL compiler for ASIC design Cadence Design Systems Inc. announced that Toshiba America Electronic Components Inc. (TAEC) has introduced a design kit to support its custom System-on-Chip (SoC) and ASIC customers using Cadence Encounter RTL compiler synthesis. |
2006-07-01 | Tool suite handles design complexity Altera Corp. recently launched its Quartus 6.0 tool suite, which includes a timing analyzer that's said to pave the way for next-generation 65nm FPGAs. |
2007-09-03 | Tips for successful structured ASIC designs The use of structured ASIC for custom IC design is an increasingly attractive option. This article provides useful tips for structured ASIC designs. |
2000-02-11 | Timing-Driven Flow (TDF) SLI ASIC design flow with commercial EDA tools The Timing-Driven Flow (TDF) is the first state-of-the-art design methodology based on open EDA tools and standards to successfully address the challenge of deep sub-micron timing convergence. Without TDF it is not uncommon for a high-gate-count, high-complexity design with tight timing specifications to go through 10-20 iterations between synthesis and layout and still fail to meet timing. This application note describes the function of the TDF in an ASIC application. |
2002-02-13 | Tianjin University to establish design center for CMOS image sensors Tianjin University will establish an ASIC design center that will focus in the design and development of CMOS image sensors. |
2006-02-27 | TI upgrades Pyramid ASIC design kit Texas Instruments announced the release of version 5 of the Pyramid ASIC design kit, targeting telecommunications, consumer and wireless infrastructure markets. |
2003-04-08 | Tera Systems technology enhances IBM ASIC design flow Tera Systems Inc. has announced that TeraForm RTL Silicon Virtual Prototype (SVP) has been integrated into the IBM Blue Logic MidRange ASIC design flow. |
2004-03-16 | Synthesis methods for ASIC, FPGA designs Design methodologies that employ cross-implementation EDA technology such as the MultiPoint provide the flexibility to implement a design in the best possible medium |
2005-07-01 | Synplicity software optimized for Fujitsu's AccelArray ASIC devices Fujitsu Ltd, Fujitsu Microelectronics America Inc. (FMA) and Synplicity Inc. announced Synplicity's new Amplify AccelArray Pro software, a physical synthesis solution optimized for Fujitsu's AccelArray structured ASIC devices |
2007-06-05 | Synplicity acquires Swedish ASIC prototyping firm Synplicity is acquiring Hardi Electronics, the Swedish FPGA-based ASIC prototyping specialist, for $24.2 million in cash |
2003-02-27 | Synopsys technology enhances TI ASIC design flow Texas Instruments Inc.'s ASIC division has completed two multi-million gate designs using Synopsys Inc.'s Physical Compiler |
2007-05-16 | Survey: Taiwan IC design aims for high-end CE The "2007 Taiwan IC Design House Survey" revealed a maturing chip design industry that's ready to take on more complex challenges to carve a name for itself in this highly competitive business |
2004-06-01 | Startup offers new 'route' to IC design Silicon Design Systems has revealed its plan to release its K-Route tool later this year |
2007-02-15 | ST adopts Synopsys compiler for ASIC design STMicroelectronics has deployed Synopsys Inc.'s Design Compiler topographical technology in its 90nm and 65nm ASIC design flow to eliminate design iterations and streamline the overall design cycle for its internal design groups and external customers. |
2016-01-18 | Speed IoT ASIC design using platforms Using a platform approach to custom silicon design can substantially enhance functionality and offer greater design flexibility |
2008-04-28 | SMIC-ASTRI team yields dual-mode UWB MAC ASIC SMIC and ASTRI have collaborated to provide the world's first dual-mode UWB MAC IC using SMIC's 0.13?m mix-mode CMOS technology. |
2002-06-26 | Slump in ASIC designs hits IP suppliers The number of ASIC designs has collapsed, with potentially serious implications for the intellectual property market |
2011-01-10 | Simplify automotive ASIC design with FMEA Learn about failure modes and effects analysis (FMEA), an essential tool to examine all aspects of a product specification. |
2002-10-28 | Shenzhen STS Micro, Tsinghua University to co-establish ASIC center Shenzhen STS Microelectronics and Shenzhen Graduate School of Tsinghua University have collaborated to establish a joint ASIC Research Center in Shenzhen, China |
2006-06-02 | Reborn Micro Magic offers EDA, IC design services The original founders of Micro Magic Inc. decided to restart their company, and they're back in business last month with services and revamped tools. |
2003-03-19 | R&D center in China to utilize Synopsys IC design tools Synopsys Inc. has agreed to donate IC design tools to the High Technology Research and Development Center of the Chinese Ministry of Science and Technology |
2012-05-16 | Quick fix for pesky FPGA design errors Know the significance of hierarchical design and fast error resolution in achieving a working design with fewer design iterations |
2001-04-15 | Process design kits take aim at custom ICs This technical article describes Cadence Design Systems' process design kits for 0.25?m and 0.18?m process simulations |
2011-09-19 | Power Silicon's SoC design earns patent win Open-Silicon has earned a patent win for its low power ASIC design process through design-specific library augmentation. |
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